riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
9,453 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

9453 Commits

Author SHA1 Message Date
Claire Wolf d834cc7afb Add '=' selection pattern prefix for non-blackbox only patterns 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-21 14:23:24 +02:00
Claire Wolf 27506d2aeb Improve net priorities in EDIF back-end 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-21 12:35:25 +02:00
David Shah abf81c7639 sim: Fix handling of constant-connected cell inputs at startup 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-21 08:58:52 +01:00
whitequark abc8f1fcb6
Merge pull request #1961 from whitequark/paramod-original-name 
ast, rpc: record original name of $paramod\* as \hdlname attribute
 2020-04-21 01:43:20 +00:00
Eddie Hung 38ee59184c tests: remove write_ilang 2020-04-20 15:42:29 -07:00
Eddie Hung d32e56a3d1
Merge pull request #1975 from dh73/claire/bitselwrite 
Adding tests to Claire/bitselwrite branch
 2020-04-20 15:34:31 -07:00
Eddie Hung caf4071c8b Remove '-ignore_unknown_cells' option from 'sat' 2020-04-20 11:58:23 -07:00
Eddie Hung a1573058e9 Simplify test case script 2020-04-20 11:54:10 -07:00
Eddie Hung 99a0958601 Remove ununsed files 2020-04-20 11:53:48 -07:00
Eddie Hung c506da3819
Merge pull request #1972 from YosysHQ/eddie/bug1970 
abc9_ops: -prep_lut to be more robust
 2020-04-20 11:39:13 -07:00
Eddie Hung 3d7b983351 abc9: tolerate ABC nonzero exit code if output.aig; write before &mfs 
Re-enable mfs for xilinx/ecp5 speculatively -- if it fails, use pre-mfs
result
 2020-04-20 11:26:11 -07:00
diego 22f440506b Modifications of tests as per Eddie's request 2020-04-20 12:45:35 -05:00
Eddie Hung a998a4155d xilinx/ecp5: disable abc9's "&mfs" optimisation 
Can sometimes fire an assertion, e.g. #1962
 2020-04-20 10:30:10 -07:00
Eddie Hung 8c992ca47f abc9: -prep_lut to be more robust 2020-04-20 09:39:35 -07:00
Eddie Hung 34d8ff8b56 abc9: add testcase reduced from #1970 2020-04-20 09:38:29 -07:00
Claire Wolf ee5067e864 Ignore conflicting keep attributes, unless asked not to. Fixes #1733 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-20 16:00:37 +02:00
Claire Wolf ae115fa3aa
Merge pull request #1964 from YosysHQ/claire/sformatf 
Extend support for format strings in Verilog front-end
 2020-04-20 14:51:40 +02:00
Alberto Gonzalez ecaa892e35
Add rvalue-reference-accepting `entry_t` constructor for `pool`. 2020-04-20 05:37:10 +00:00
Alberto Gonzalez 95b94ad19b
In `pool`, construct `entry_t`s in-place and add an rvalue-accepting-and-forwarding `insert()` method. 2020-04-20 02:18:30 +00:00
whitequark 2b1fb8c0a0
Merge pull request #1967 from whitequark/cxxrtl-blackbox-attributes 
cxxrtl: provide attributes to black box factories, too
 2020-04-19 19:59:42 +00:00
whitequark bf0f96b847 cxxrtl: provide attributes to black box factories, too. 
Both parameters and attributes are necessary because the parameters
have to be the same between every instantiation of the cell, but
attributes may well vary. For example, for an UART PHY, the type
of the PHY (tty, pty, socket) would be a parameter, but configuration
of the implementation specified by the type (socket address) would
be an attribute.
 2020-04-19 16:30:54 +00:00
Claire Wolf 35990b95ec Extend support for format strings in Verilog front-end 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-18 14:08:51 +02:00
whitequark c98cde8842
Merge pull request #1963 from whitequark/cxxrtl-blackboxes 
cxxrtl: add support for simple and templated C++ black boxes
 2020-04-18 09:21:14 +00:00
whitequark 63d2a30857 cxxrtl: add templated black box support. 2020-04-18 08:04:57 +00:00
whitequark ab4297c326 cxxrtl: make eval() and commit() inline in blackboxes. 
This change is a preparation for template blackboxes. It has no
effect on current generated code.
 2020-04-18 04:38:50 +00:00
whitequark 2b88d9a3fe cxxrtl: add simple black box support. 
This commit adds support for replacing RTLIL modules with CXXRTL
black boxes. Black box port widths may not depend on the parameters
with which it is instantiated (yet); the parameters may only be used
to change the behavior of the black box.
 2020-04-18 04:35:10 +00:00
whitequark 8bc3cd30dc cxxrtl: use ID::X instead of ID(X). NFC. 2020-04-18 04:35:10 +00:00
whitequark 41421f5dca ast, rpc: record original name of $paramod\* as \hdlname attribute. 
The $paramod name mangling is not invertible (the \ character, which
separates the module name from the parameters, is valid in the module
name itself), which does not stop people from trying to invert it.

This commit makes it easy to invert the name mangling by storing
the original name explicitly, and fixes the firrtl backend to use
the newly introduced attribute.
 2020-04-18 03:47:28 +00:00
whitequark d42530b7bb
Merge pull request #1955 from whitequark/cxxrtl-sync_always 
cxxrtl: correctly handle `sync always` rules
 2020-04-17 21:36:59 +00:00
whitequark 67fbc00a18
Merge pull request #1952 from boqwxp/add_edge_location 
Verilog frontend: add source location in more parser rules
 2020-04-17 18:57:00 +00:00
diego 50581d5a94 Wrong fixed value 2020-04-17 10:15:22 -05:00
whitequark e7ad209b15 cxxrtl: correctly handle `sync always` rules. 
Fixes #1948.
 2020-04-17 09:43:13 +00:00
whitequark 115fc261e6
Merge pull request #1954 from YosysHQ/dave/fix-stdout-conflict 
qbfsat: Fix illegal use of 'stdout' identifier
 2020-04-17 09:07:49 +00:00
whitequark 4d1db12133
Merge pull request #1951 from whitequark/rtlil-string_attribute 
rtlil: add AttrObject::{get,set}_string_attribute, AttrObject::has_attribute
 2020-04-17 09:06:40 +00:00
David Shah 586739ecf3 qbfsat: Fix illegal use of 'stdout' identifier 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-17 08:42:39 +01:00
Alberto Gonzalez 00d74f0b9c
Set Verilog source location for explicit blocks (`begin` ... `end`). 2020-04-17 06:23:03 +00:00
Alberto Gonzalez 10a814f978
Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes. 2020-04-17 06:16:59 +00:00
whitequark c69db910ac
Merge pull request #1898 from boqwxp/locations 
Verilog frontend: add location information to parsed constants
 2020-04-17 02:27:13 +00:00
whitequark 69743aad42
Merge pull request #1864 from boqwxp/cleanup_techmap_abc 
Clean up pseudo-private member usage and simplify `passes/techmap/abc.cc`
 2020-04-17 02:25:18 +00:00
whitequark f2064c8131
Merge pull request #1888 from boqwxp/cleanup_scatter 
Clean up `passes/cmds/scatter.cc`.
 2020-04-17 02:21:23 +00:00
whitequark 5c428996a9
Merge pull request #1882 from boqwxp/cleanup_rename 
Clean up pseudo-private member usage in `passes/cmds/rename.cc`.
 2020-04-17 02:20:54 +00:00
whitequark 31e3e52988
Merge pull request #1929 from YosysHQ/eddie/select_unset 
select: add select -unset option
 2020-04-16 22:09:25 +00:00
whitequark b6f624b56b rtlil: add AttrObject::has_attribute. 2020-04-16 21:49:49 +00:00
whitequark ff7a1a1568 rtlil: add AttrObject::{get,set}_string_attribute. 
And make {get,set}_src_attribute use those functions.
 2020-04-16 21:45:29 +00:00
whitequark b4b2345a10
Merge pull request #1947 from whitequark/cxxrtl-usability 
cxxrtl: minor documentation and usability improvements
 2020-04-16 21:28:13 +00:00
Eddie Hung 9eace8f360 design: add test 2020-04-16 12:48:40 -07:00
Eddie Hung dac5adde12 design: -import to not count black/white-boxes as candidates for top 2020-04-16 12:46:07 -07:00
Eddie Hung 2ddfb61e65 select: add test for not selecting inside black/white boxes 2020-04-16 12:45:04 -07:00
Eddie Hung 47c8ee7fe4 select: do not select inside blackboxes 2020-04-16 12:23:34 -07:00
Alberto Gonzalez 9253497358
Add location information to `AST_CONSTANT` nodes. 2020-04-16 19:11:47 +00:00