Commit Graph

9453 Commits

Author SHA1 Message Date
Alberto Gonzalez 2e3647f567
Use `dict` instead of `std::map`.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-04-16 18:56:50 +00:00
Alberto Gonzalez b94f38295a
Revert to `stringf()` rather than stringstreams. 2020-04-16 18:56:50 +00:00
Alberto Gonzalez 6081c1bbd3
Clean up pseudo-private member usage in `passes/cmds/rename.cc`. 2020-04-16 18:56:50 +00:00
Alberto Gonzalez ff8be2364e
Replace `std::map` with `dict`.
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-04-16 18:49:55 +00:00
Alberto Gonzalez 0424555702
Replace pseudo-private member access to `connections_` in `passes/cmds/scatter.cc`.
Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
2020-04-16 18:49:55 +00:00
Alberto Gonzalez 0787af947f
Clean up `passes/cmds/scatter.cc`. 2020-04-16 18:49:55 +00:00
diego 87910732f1 Adding tests for dynamic part select optimisation 2020-04-16 13:31:05 -05:00
Eddie Hung 2623e335cc tests: add select -unset tests 2020-04-16 10:51:58 -07:00
Eddie Hung 254d38ca67 select: add select -unset option 2020-04-16 10:51:58 -07:00
Eddie Hung 8d3f6d0d79
Merge pull request #1928 from YosysHQ/eddie/design_delete
kernel: add design -delete option
2020-04-16 10:51:09 -07:00
whitequark c2804a68c2
Merge pull request #1896 from boqwxp/read_stdin_repl
Frontend: allow reading file input from stdin, like a REPL heredoc mode
2020-04-16 17:18:29 +00:00
Claire Wolf 7a434cdd7b
Merge pull request #1797 from epfl-vlsc/firrtl_backend_fileinfo
Keep file information when emitting firrtl
2020-04-16 18:50:43 +02:00
whitequark 06c0338f2c cxxrtl: make ROMs writable, document memory::operator[].
There is no practical benefit from using `const memory` for ROMs;
it uses an std::vector internally, which prevents contemporary
compilers from constant-propagating ROM contents. (It is not clear
whether they are permitted to do so.)

However, there is a major benefit from using non-const `memory` for
ROMs, which is the ability to dynamically fill the ROM for each
individual simulation.
2020-04-16 16:45:54 +00:00
whitequark 9043632dcc cxxrtl: fix misleading example, caution about race conditions.
Fixes #1944.
2020-04-16 16:45:54 +00:00
whitequark 58e89cd368 cxxrtl: remove inaccurate comment. NFC. 2020-04-16 16:45:54 +00:00
David Shah 1664bcda12 ecp5: Force SIGNED ports to be 1 bit
Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 16:38:19 +01:00
Eddie Hung aa552cefa3
Merge pull request #1927 from YosysHQ/eddie/design_remove_assert
kernel: Design::remove(RTLIL::Module *) to check refcount_modules_
2020-04-16 08:06:12 -07:00
Eddie Hung e8a841467f tests: add design -delete tests 2020-04-16 08:05:18 -07:00
Eddie Hung a9ec0defb9 kernel: add design -delete option 2020-04-16 08:05:18 -07:00
whitequark 90a1c6b6a4
Merge pull request #1915 from boqwxp/dict_move_semantics
kernel: Add `dict` support for rvalue references and C++11 move semantics.
2020-04-16 13:29:13 +00:00
whitequark 2ee028dcf1
Merge pull request #1900 from Xiretza/suppress-makefile-echo
Suppress output of Makefile.conf when printing source versions
2020-04-16 13:28:34 +00:00
whitequark e1f5145afa
Merge pull request #1937 from hzeller/consexpr-opportunity
Use static constexpr instead of static const where possible.
2020-04-16 13:28:03 +00:00
David Shah 2b57c06360
Merge pull request #1943 from YosysHQ/dave/fix-1919
ast: Fix handling of identifiers in the global scope
2020-04-16 13:48:20 +01:00
Claire Wolf e86ba3b94d Make mask-and-shift the default for bitselwrite
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-16 12:11:52 +02:00
Claire Wolf e1fb12a4b9 Add LookaheadRewriter for proper bitselwrite support
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-16 12:11:07 +02:00
Marcelina Kościelnicka 2f8541a92e opt_expr: Fix X and CO outputs for $alu identity-mapping rules. 2020-04-16 11:48:29 +02:00
David Shah 4d02505820 ast: Fix handling of identifiers in the global scope
Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 10:30:07 +01:00
Alberto Gonzalez 5eb1f83d2d
Rename overloaded `insert()` to `emplace()` and add overloaded versions for all possible lvalue/rvalue combinationsfor its arguments. 2020-04-16 03:54:33 +00:00
Alberto Gonzalez 76c9e1c265
Use script-style heredoc syntax for REPL heredocs. 2020-04-15 16:15:51 +00:00
Alberto Gonzalez b5ecbbef94
Allow reading file input from stdin, improving REPL experience. 2020-04-15 16:15:50 +00:00
Claire Wolf 4711fea6c0 Improved rewrite code for writing to bit slice (disabled for now)
This adds the new rewrite rule. But it's still missing a check that makes
sure the new rewrite rule is actually a valid substitute in the always
block being processed. Therefore the new rewrite rule is just disabled
for now.

Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-15 17:44:37 +02:00
Miodrag Milanović 3c4758c60e
Merge pull request #1894 from YosysHQ/mingw_fix
Fix compile for mingw
2020-04-15 17:43:31 +02:00
Eddie Hung dc3d432aaa
Merge pull request #1916 from YosysHQ/eddie/kernel_makeblackbox
kernel: Module::makeblackbox() to clear connections too
2020-04-15 08:42:39 -07:00
Eddie Hung 33b0ac9269
Merge pull request #1933 from YosysHQ/eddie/zinit_more
zinit: handle $__DFFS?E?_[NP][NP][01] too
2020-04-15 08:36:25 -07:00
N. Engelhardt 0b7a5879e5
Merge pull request #1830 from boqwxp/qbfsat
Add `qbfsat` command to integrate exists-forall solving and specialization
2020-04-15 17:33:50 +02:00
Marcelina Kościelnicka 53ba3cf718 Fix the truth table for $_SR_* cells.
This brings the documented behavior for these cells in line with
$_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S.
The models were already reflecting that behavior.

Also get rid of sim-synth mismatch in the models while we're at it.
2020-04-15 17:17:48 +02:00
David Shah 7ad8b24280
Merge pull request #1897 from YosysHQ/dave/bram-rejection-fix
memory_bram: Fix ignorance of valid, matched rules
2020-04-15 16:10:38 +01:00
Miodrag Milanovic bc21e58bb5 Fix compile for mingw 2020-04-15 16:38:09 +02:00
Marcelina Kościelnicka 38a0c30d65 Get rid of dffsr2dff.
This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part.  Thus, it never
actually does anything and can be safely removed.
2020-04-15 16:22:37 +02:00
Marcelina Kościelnicka 85166633bc opt_clean: Add missing assignments to opt.did_something. 2020-04-15 16:20:56 +02:00
whitequark 2d436bc4f1
Merge pull request #1918 from whitequark/simplify-improve_enum
ast/simplify: improve enum handling
2020-04-15 14:16:50 +00:00
Dan Ravensloft 43cc6bd8a1 synth_intel_alm: VQM support 2020-04-15 16:15:25 +02:00
whitequark 2106f78bb1 ast/simplify: improve enum handling.
Before this commit, enum values were serialized as attributes of form
  \enum_<width>_<value>
where <value> was a decimal signed integer.

This has multiple drawbacks:
  * Enums with large values would be hard to process for downstream
    tooling that cannot parse arbitrary precision decimals. (In fact
    Yosys also did not correctly process enums with large values,
    and would overflow `int`.)
  * Enum value attributes were not confined to their own namespace,
    making it harder for downstream tooling to enumerate all such
    attributes, as opposed to looking up any specific value.
  * Enum values could not include x or z, which are explicitly
    permitted in the SystemVerilog standard.

After this commit, enum values are serialized as attributes of form
  \enum_value_<value>
where <value> is a bit sequence of the appropriate width.
2020-04-15 14:14:50 +00:00
Marcelina Kościelnicka d7da491002 setundef: Improve error messages.
Fixes #1092.
2020-04-15 16:13:28 +02:00
Marcelina Kościelnicka 3611e7c864 json: Update format documentation.
Fixes #1693.
2020-04-15 16:12:14 +02:00
Claire Wolf 4ee8fc1473
Merge pull request #1930 from YosysHQ/claire/fix1876
Fix handling of ternary with constant condition
2020-04-15 16:01:19 +02:00
Dan Ravensloft 2e37e62e6b synth_intel_alm: alternative synthesis for Intel FPGAs
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
2020-04-15 11:40:41 +02:00
Marcelina Kościelnicka 4c52691a58 abc9_ops: Add a check ensuring that connected port actually exists. 2020-04-15 08:11:15 +02:00
whitequark a143f04e7d
Merge pull request #1932 from YosysHQ/dave/cxxrtl-unclocked-read
cxxrtl: Fix handling of unclocked memory read ports
2020-04-15 05:34:29 +00:00
Henner Zeller 5c6e681673 Use static constexpr instead of static const where possible.
In particular inside class declarations, a static const
assignment is technically not a definition, while constexpr is.

Signed-off-by: Henner Zeller <h.zeller@acm.org>
2020-04-14 14:19:38 -07:00