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303 Commits

Author SHA1 Message Date
David Shah e70e4afb60 sv: Fix typedefs in packages 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah c962951612 sv: Fix typedef parameters 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
David Shah f6b5e47e40 sv: Switch parser to glr, prep for typedef 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-03 09:54:14 +01:00
Clifford Wolf 25b08b1afd Fix handling of range selects on loop variables, fixes #1372 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-16 11:25:37 +02:00
Clifford Wolf 25e5fbac90 Properly construct $live and $fair cells from "if (...) assume/assert (s_eventually ...)" 
Fixes https://github.com/YosysHQ/SymbiYosys/issues/59

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-09-02 22:56:38 +02:00
Eddie Hung fe1b2337fd Do not propagate mem2reg attribute through to result 2019-08-22 16:57:59 -07:00
Eddie Hung a6776ee35e mem2reg to preserve user attributes and src 2019-08-21 13:36:01 -07:00
Eddie Hung 6d77236f38 substr() -> compare() 2019-08-07 12:20:08 -07:00
Eddie Hung e6d5147214 Merge remote-tracking branch 'origin/master' into eddie/cleanup 2019-08-07 11:11:50 -07:00
Eddie Hung ee7c970367 IdString::str().substr() -> IdString::substr() 2019-08-06 19:08:33 -07:00
Clifford Wolf f1f5b4e375 Fix handling of functions/tasks without top-level begin-end block, fixes #1231 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-08-06 18:06:14 +02:00
Clifford Wolf d187be39d6 Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968 2019-05-06 15:41:13 +02:00
Clifford Wolf 6bbe2fdbf3 Add splitcmplxassign test case and silence splitcmplxassign warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 10:01:54 +02:00
Clifford Wolf 59d74a3348 Re-enable "final loop assignment" feature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-05-01 09:02:39 +02:00
Clifford Wolf e35fe1344d Disabled "final loop assignment" feature 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 20:22:50 +02:00
Clifford Wolf 9af825e31e Add final loop variable assignment when unrolling for-loops, fixes #968 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-30 15:03:32 +02:00
Clifford Wolf 4ad0ea5c3c Determine correct signedness and expression width in for loop unrolling, fixes #370 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 18:19:02 +02:00
Zachary Snow 5855024ccc support repeat loops with constant repeat counts outside of constant functions 2019-04-09 12:28:32 -04:00
Clifford Wolf 638be461c3 Fix mem2reg handling of memories with upto data ports, fixes #888 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-21 22:21:17 +01:00
Zachary Snow a5f4b83637 fix local name resolution in prefix constructs 2019-03-18 20:43:20 -04:00
Clifford Wolf d25a0c8ade Improve handling of memories used in mem index expressions on LHS of an assignment 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:12:02 +01:00
Clifford Wolf a4ddc569b4 Remove outdated "blocking assignment to memory" warning 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:10:55 +01:00
Clifford Wolf ab5b50ae3c Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-12 20:09:47 +01:00
Clifford Wolf cebd21aa96
Merge pull request #858 from YosysHQ/clifford/svalabels 
Add support for using SVA labels in yosys-smtbmc console output
 2019-03-09 11:14:57 -08:00
Clifford Wolf a330c68363 Fix handling of task output ports in clocked always blocks, fixes #857 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 22:44:37 -08:00
Clifford Wolf 22ff60850e Add support for SVA labels in read_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-07 11:17:32 -08:00
Clifford Wolf ae9286386d Only run derive on blackbox modules when ports have dynamic size 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 12:36:46 -08:00
Clifford Wolf ce6695e22c Fix $global_clock handling vs autowire 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 10:38:13 -08:00
Clifford Wolf 5d93dcce86 Fix $readmem[hb] for mem2reg memories, fixes #785 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-02 09:58:20 -08:00
Clifford Wolf 7cfae2c52f Use mem2reg on memories that only have constant-index write ports 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-03-01 13:35:09 -08:00
Clifford Wolf 1816fe06af Fix handling of defparam for when default_nettype is none 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-24 20:09:41 +01:00
Clifford Wolf 23148ffae1 Fixes related to handling of autowires and upto-ranges, fixes #814 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 18:40:11 +01:00
Clifford Wolf 974927adcf Fix handling of expression width in $past, fixes #810 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-02-21 17:55:33 +01:00
Clifford Wolf fdf7c42181 Fix segfault in AST simplify 
(as proposed by Dan Gisselquist)

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-12-18 17:49:38 +01:00
Sylvain Munaut 86ce43999e Make return value of $clog2 signed 
As per Verilog 2005 - 17.11.1.

Fixes #708

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
 2018-11-24 18:49:23 +01:00
Clifford Wolf 64e0582c29 Various indenting fixes in AST front-end (mostly space vs tab issues) 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-04 10:19:32 +01:00
ZipCPU 39f891aebc Make and dependent upon LSB only 2018-11-03 13:39:32 -04:00
Clifford Wolf d86ea6badd Do not generate "reg assigned in a continuous assignment" warnings for "rand reg" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-11-01 15:25:24 +01:00
Clifford Wolf f24bc1ed0a
Merge pull request #659 from rubund/sv_interfaces 
Support for SystemVerilog interfaces and modports
 2018-10-18 10:58:47 +02:00
Clifford Wolf 38dbb44fa0
Merge pull request #638 from udif/pr_reg_wire_error 
Fix issue #630
 2018-10-17 12:13:18 +02:00
Ruben Undheim 75009ada3c Synthesis support for SystemVerilog interfaces 
This time doing the changes mostly in AST before RTLIL generation
 2018-10-12 21:11:36 +02:00
Dan Gisselquist 62424ef3de Add read_verilog $changed support 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-10-01 19:41:35 +02:00
Clifford Wolf 9f9fe94b35 Fix handling of $past 2nd argument in read_verilog 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-30 18:43:35 +02:00
Udi Finkelstein 80a07652f2 Fixed issue #630 by fixing a minor typo in the previous commit 
(as well as a non critical minor code optimization)
 2018-09-25 00:32:57 +03:00
Udi Finkelstein c693f595c5 Merge branch 'master' into pr_reg_wire_error 2018-09-18 01:27:01 +03:00
Udi Finkelstein f6fe73b31f Fixed remaining cases where we check fo wire reg/wire incorrect assignments 
on Yosys-generated assignments.
In this case, offending code was:

module top(input in, output out);
function func;
  input arg;
  func = arg;
endfunction
assign out = func(in);
endmodule
 2018-09-18 01:23:40 +03:00
Clifford Wolf d8e40c75eb
Merge pull request #590 from hzeller/remaining-file-error 
Fix remaining log_file_error(); emit dependent file references in new…
 2018-08-15 14:01:34 +02:00
Clifford Wolf 3d27c1cc80
Merge pull request #513 from udif/pr_reg_wire_error 
Add error checking for reg/wire/logic misuse - PR now passes 'make test' (plus a new test)
 2018-08-15 13:35:41 +02:00
Henner Zeller 3101b9b8c9 Fix remaining log_file_error(); emit dependent file references in new line. 
There are some places that reference dependent file locations ("this function was
called from ..."). These are now in a separate line for ease of jumping to
it with the editor (behaves similarly to compilers that emit dependent
messages).
 2018-07-20 18:52:52 -07:00
Henner Zeller 68b5d0c3b1 Convert more log_error() to log_file_error() where possible. 
Mostly statements that span over multiple lines and haven't been
caught with the previous conversion.
 2018-07-20 09:37:44 -07:00
Henner Zeller b5ea598ef6 Use log_file_warning(), log_file_error() functions. 
Wherever we can report a source-level location.
 2018-07-20 08:19:06 -07:00
Udi Finkelstein 73d426bc87 Modified errors into warnings 
No longer false warnings for memories and assertions
 2018-06-05 18:03:22 +03:00
Udi Finkelstein 2b9c75f8e3 This PR should be the base for discussion, do not merge it yet! 
It correctly detects reg/wire mix and incorrect use on blocking,nonblocking assignments within blocks and assign statements.

What it DOES'T do:
Detect registers connected to output ports of instances.

Where it FAILS:
memorty nonblocking assignments causes spurious (I assume??) errors on yosys-generated "_ADDR", "_DATA", "EN" signals.

You can test it with tests/simple/reg_wire_error.v (look inside for the comments to enable/disable specific lines)
 2018-03-11 23:09:34 +02:00
Clifford Wolf eb67a7532b Add $allconst and $allseq cell types 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-02-23 13:14:47 +01:00
Clifford Wolf a96c775a73 Add support for "yosys -E" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-01-07 16:36:13 +01:00
Clifford Wolf 8364f509e3 Fix error handling for nested always/initial 2017-12-02 18:52:05 +01:00
Clifford Wolf bc80426d45 Remove some dead code 2017-10-10 12:00:48 +02:00
Clifford Wolf caa78388cd Allow $past, $stable, $rose, $fell in $global_clock blocks 2017-10-10 11:59:32 +02:00
Clifford Wolf dbfd8460a9 Allow $size and $bits in verilog mode, actually check test case 2017-09-29 11:56:43 +02:00
Udi Finkelstein e951ac0dfb $size() now works correctly for all cases! 
It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
 2017-09-26 20:34:24 +03:00
Udi Finkelstein 6ddc6a7af4 $size() seems to work now with or without the optional parameter. 
Multidimensional arrays still don't work. I suspect the problem is that the array is flattened into a 1D array before $size() is evaluated.
 2017-09-26 19:18:25 +03:00
Udi Finkelstein 7e391ba904 enable $bits() and $size() functions only when the SystemVerilog flag is enabled for read_verilog 2017-09-26 09:19:56 +03:00
Udi Finkelstein 2dea42e903 Added $bits() for memories as well. 2017-09-26 09:11:25 +03:00
Udi Finkelstein 17f8b41605 $size() now works with memories as well! 2017-09-26 08:36:45 +03:00
Udi Finkelstein 64eb8f29ad Add $size() function. At the moment it works only on expressions, not on memories. 2017-09-26 06:25:42 +03:00
Clifford Wolf 5f1d0b1024 Add $live and $fair cell types, add support for s_eventually keyword 2017-02-25 10:36:39 +01:00
Clifford Wolf 4fb8007171 Fix incorrect "incompatible re-declaration of wire" error in tasks/functions 2017-02-14 15:10:59 +01:00
Clifford Wolf 3928482a3c Add $cover cell type and SVA cover() support 2017-02-04 14:14:26 +01:00
Clifford Wolf 78f65f89ff Fix bug in AstNode::mem2reg_as_needed_pass2() 2017-01-15 13:52:50 +01:00
Clifford Wolf 2d32c6c4f6 Fixed handling of local memories in functions 2017-01-05 13:19:03 +01:00
Clifford Wolf 81a9ee2360 Added handling of local memories and error for local decls in unnamed blocks 2017-01-04 16:03:04 +01:00
Clifford Wolf dfb461fe52 Added Verilog $rtoi and $itor support 2017-01-03 17:40:58 +01:00
Clifford Wolf 70d7a02cae Added support for hierarchical defparams 2016-11-15 13:35:19 +01:00
Clifford Wolf 2874914bcb Fixed anonymous genblock object names 2016-11-04 07:46:30 +01:00
Clifford Wolf 56e2bb88ae Some fixes in handling of signed arrays 2016-11-01 23:17:43 +01:00
Clifford Wolf bdc316db50 Added $anyseq cell type 2016-10-14 15:24:03 +02:00
Clifford Wolf aaa99c35bd Added $past, $stable, $rose, $fell SVA functions 2016-09-19 01:30:07 +02:00
Clifford Wolf 97583ab729 Avoid creation of bogus initial blocks for assert/assume in always @* 2016-09-06 17:34:42 +02:00
Clifford Wolf 6f41e5277d Removed $aconst cell type 2016-08-30 19:09:56 +02:00
Clifford Wolf eae390ae17 Removed $predict again 2016-08-28 21:35:33 +02:00
Clifford Wolf 450f6f59b4 Fixed bug with memories that do not have a down-to-zero data width 2016-08-22 14:27:46 +02:00
Clifford Wolf 82a4a0230f Another bugfix in mem2reg code 2016-08-21 13:23:58 +02:00
Clifford Wolf fe9315b7a1 Fixed finish_addr handling in $readmemh/$readmemb 2016-08-20 13:47:46 +02:00
Clifford Wolf f6629b9c29 Optimize memory address port width in wreduce and memory_collect, not verilog front-end 2016-08-19 18:38:25 +02:00
Clifford Wolf 4056312987 Added $anyconst and $aconst 2016-07-27 15:41:22 +02:00
Clifford Wolf 7fef5ff104 Using $initstate in "initial assume" and "initial assert" 2016-07-21 14:37:28 +02:00
Clifford Wolf 5c166e76e5 Added $initstate cell type and vlog function 2016-07-21 14:23:22 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Clifford Wolf 9a101dc1f7 Fixed mem assignment in left-hand-side concatenation 2016-07-08 14:31:06 +02:00
Clifford Wolf ee071586c5 Fixed access-after-delete bug in mem2reg code 2016-05-27 17:25:33 +02:00
Clifford Wolf 5a09fa4553 Fixed handling of parameters and const functions in casex/casez pattern 2016-04-21 15:31:54 +02:00
Clifford Wolf 5328a85149 Do not set "nosync" on task outputs, fixes #134 2016-03-24 12:16:47 +01:00
Clifford Wolf 4f0d4899ce Added support for $stop system task 2016-03-21 16:19:51 +01:00
Clifford Wolf e5d42ebb4d Added $display %m support, fixed mem leak in $display, fixes #128 2016-03-19 11:51:13 +01:00
Clifford Wolf ef4207d5ad Fixed localparam signdness, fixes #127 2016-03-18 12:15:00 +01:00
Clifford Wolf b6d08f39ba Set "nosync" attribute on internal task/function wires 2016-03-18 10:53:29 +01:00
Clifford Wolf bcc873b805 Fixed some visual studio warnings 2016-02-13 17:31:24 +01:00
Clifford Wolf c86fbae3d1 Fixed handling of re-declarations of wires in tasks and functions 2015-11-23 17:09:57 +01:00
Clifford Wolf 7ae3d1b5a9 More bugfixes in handling of parameters in tasks and functions 2015-11-12 13:02:36 +01:00