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9765 Commits

Author SHA1 Message Date
Marcelina Kościelnicka 38a0c30d65 Get rid of dffsr2dff. 
This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part.  Thus, it never
actually does anything and can be safely removed.
 2020-04-15 16:22:37 +02:00
Marcelina Kościelnicka 85166633bc opt_clean: Add missing assignments to opt.did_something. 2020-04-15 16:20:56 +02:00
whitequark 2d436bc4f1
Merge pull request #1918 from whitequark/simplify-improve_enum 
ast/simplify: improve enum handling
 2020-04-15 14:16:50 +00:00
Dan Ravensloft 43cc6bd8a1 synth_intel_alm: VQM support 2020-04-15 16:15:25 +02:00
whitequark 2106f78bb1 ast/simplify: improve enum handling. 
Before this commit, enum values were serialized as attributes of form
  \enum_<width>_<value>
where <value> was a decimal signed integer.

This has multiple drawbacks:
  * Enums with large values would be hard to process for downstream
    tooling that cannot parse arbitrary precision decimals. (In fact
    Yosys also did not correctly process enums with large values,
    and would overflow `int`.)
  * Enum value attributes were not confined to their own namespace,
    making it harder for downstream tooling to enumerate all such
    attributes, as opposed to looking up any specific value.
  * Enum values could not include x or z, which are explicitly
    permitted in the SystemVerilog standard.

After this commit, enum values are serialized as attributes of form
  \enum_value_<value>
where <value> is a bit sequence of the appropriate width.
 2020-04-15 14:14:50 +00:00
Marcelina Kościelnicka d7da491002 setundef: Improve error messages. 
Fixes #1092.
 2020-04-15 16:13:28 +02:00
Marcelina Kościelnicka 3611e7c864 json: Update format documentation. 
Fixes #1693.
 2020-04-15 16:12:14 +02:00
Claire Wolf 4ee8fc1473
Merge pull request #1930 from YosysHQ/claire/fix1876 
Fix handling of ternary with constant condition
 2020-04-15 16:01:19 +02:00
Dan Ravensloft 2e37e62e6b synth_intel_alm: alternative synthesis for Intel FPGAs 
By operating at a layer of abstraction over the rather clumsy Intel primitives,
we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping.

This also makes the primitives much easier to manipulate, and more descriptive
(no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
 2020-04-15 11:40:41 +02:00
Marcelina Kościelnicka 4c52691a58 abc9_ops: Add a check ensuring that connected port actually exists. 2020-04-15 08:11:15 +02:00
whitequark a143f04e7d
Merge pull request #1932 from YosysHQ/dave/cxxrtl-unclocked-read 
cxxrtl: Fix handling of unclocked memory read ports
 2020-04-15 05:34:29 +00:00
Henner Zeller 5c6e681673 Use static constexpr instead of static const where possible. 
In particular inside class declarations, a static const
assignment is technically not a definition, while constexpr is.

Signed-off-by: Henner Zeller <h.zeller@acm.org>
 2020-04-14 14:19:38 -07:00
Eddie Hung 383fe4a4bc tests: zinit for new types 2020-04-14 13:08:37 -07:00
Eddie Hung a8ab74285b zinit: handle $__DFFS?E?_[NP][NP][01] too 2020-04-14 13:08:23 -07:00
Marcelina Kościelnicka 6c16fd760b opt_expr: Add more $alu optimizations. 
Detect the places in the $alu where the carry bit is constant (due to
const A[i] == B[i] ^ BI) and split it into smaller $alu at these points.

Also, make the existing const-carry detection for low bits more generic
(now handles cases where both BI and CI are constant, but not equal to
one another).

Fixes #1912.
 2020-04-14 21:48:13 +02:00
David Shah 3b85b7c57a cxxrtl: Fix handling of unclocked memory read ports 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-14 20:39:13 +01:00
Eddie Hung e7121cc15c tests: add testcases from #1876 2020-04-14 12:39:10 -07:00
Claire Wolf 9b4dab397e Fix 5bba9c3, closes #1876 
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
 2020-04-14 21:05:07 +02:00
Marcelina Kościelnicka 7a36728b2f dffinit: Avoid setting init parameter to zero-length value. 
Fixes #1704.
 2020-04-14 19:52:19 +02:00
Eddie Hung 75bb2c8c24 design: do not delete when iterating over Design::modules() directly 2020-04-14 10:43:05 -07:00
Eddie Hung 635b2b8939 kernel: Design::remove(RTLIL::Module *) to check refcount_modules_ 2020-04-14 09:31:06 -07:00
Eddie Hung 3a27906ac6 abc9_exe: verify -> &verify -s 2020-04-14 08:21:26 -07:00
Eddie Hung 843201ec96 techmap: fix error message 2020-04-14 08:17:02 -07:00
whitequark d8f2a1fda0
Merge pull request #1922 from whitequark/write_cxxrtl-disconnected-outputs 
write_cxxrtl: ignore disconnected module ports
 2020-04-14 14:37:48 +00:00
whitequark 7025881a5e
Merge pull request #1921 from whitequark/write_cxxrtl-separate-compilation 
write_cxxrtl: enable separate compilation
 2020-04-14 13:53:52 +00:00
Eddie Hung 759283fa65
Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check 
xaiger: add check for $__ABC9_DELAY model
 2020-04-14 06:01:55 -07:00
whitequark f41c7ccfff
Merge pull request #1879 from jjj11x/jjj11x/package_decl 
support using previously declared types/localparams/parameters in package
 2020-04-14 12:40:00 +00:00
whitequark 0e1beb6f30
Merge pull request #1880 from jjj11x/duplicate_enum 
duplicated enum item names should result in an error
 2020-04-14 12:39:28 +00:00
whitequark 0d0bf9c4a2 write_cxxrtl: ignore disconnected module ports. 
E.g. port `q` in `submod x(.p(p), .q());`.

Fixes #1920.
 2020-04-14 12:36:20 +00:00
whitequark 9c64d37a4c write_verilog: fix precondition check. 2020-04-14 12:12:50 +00:00
whitequark 102fb5424f write_cxxrtl: enable separate compilation. 
This commit makes it possible to use several cxxrtl-generated files
in one application, as well as compiling cxxrtl-generated code as
a separate compilation unit.
 2020-04-14 12:07:58 +00:00
Eddie Hung 9547d8c13e kernel: Module::makeblackbox() to clear connections too 2020-04-13 20:37:22 -07:00
Alberto Gonzalez 4ccaf048a5
Simplify `passes/techmap/abc.cc` and remove superfluous `RTLIL::SigSpec` constructions. 
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
 2020-04-14 02:39:44 +00:00
Eddie Hung 0808318d55 xaiger: add check for $__ABC9_DELAY model 2020-04-13 19:11:23 -07:00
Eddie Hung f44b287f8e
Merge pull request #1568 from YosysHQ/eddie/fix_zinit 
zinit: fixes for $_DFF_[NP][NP][01]_and $adff cells with init = 1'b1
 2020-04-13 18:33:42 -07:00
Alberto Gonzalez c479fdeb85
Add `dict` support for rvalue references and C++11 move semantics. 2020-04-13 23:52:16 +00:00
Eddie Hung b75c5bf743 zinit: resolve one more comment by @mwkmwkmwk 2020-04-13 15:25:37 -07:00
Eddie Hung c6afce7638 zinit: fix review comments from @mwkmwkmwk 2020-04-13 15:16:51 -07:00
Eddie Hung 091297b9ee tests: zinit on $adff 2020-04-13 14:29:44 -07:00
Eddie Hung 70bca35f9c zinit: operate on $adff, erase (* init *) entries on consumption 2020-04-13 14:28:53 -07:00
Eddie Hung 1cdfdbc6d1 Fix S/R comment; thanks @mwkmwkmwk 2020-04-13 13:45:18 -07:00
Eddie Hung 4617aa8ccd zinit to transform set/reset value of $_DFF_[NP][NP][01]_ 2020-04-13 13:45:18 -07:00
Eddie Hung 3c5a9411b1 Add testcase for $_DFF_[NP][NP][01]_ 2020-04-13 13:16:49 -07:00
Eddie Hung b97a9cd3f3 Supress error for unhandled \init if whole module selected 2020-04-13 13:16:49 -07:00
Marcelina Kościelnicka 840bb17089 opt_expr: Optimize multiplications with low 0 bits in operands. 
Fixes #1500.
 2020-04-13 16:52:22 +02:00
whitequark 5448f9c85d
Merge pull request #1910 from boqwxp/cleanup_ilang_parser 
Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
 2020-04-13 08:40:45 +00:00
Alberto Gonzalez 8a84674a42
Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`. 2020-04-13 04:22:00 +00:00
Xiretza 7f1d83c5db Add .gitignore to tests/select/ 2020-04-12 22:45:45 +02:00
David Shah 87555c44d5
Merge pull request #1907 from YosysHQ/dave/fix-1906 
verilog: Fix write to deleted object
 2020-04-12 21:08:02 +01:00
David Shah 0a178de1b3 verilog: Fix write to deleted object 
Signed-off-by: David Shah <dave@ds0.me>
 2020-04-12 18:49:09 +01:00