mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1568 from YosysHQ/eddie/fix_zinit
zinit: fixes for $_DFF_[NP][NP][01]_and $adff cells with init = 1'b1
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commit
f44b287f8e
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@ -57,8 +57,7 @@ struct ZinitPass : public Pass {
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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dict<SigBit, State> initbits;
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pool<SigBit> donebits;
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dict<SigBit, std::pair<State,SigBit>> initbits;
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for (auto wire : module->selected_wires())
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{
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@ -67,7 +66,6 @@ struct ZinitPass : public Pass {
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SigSpec wirebits = sigmap(wire);
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Const initval = wire->attributes.at(ID::init);
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wire->attributes.erase(ID::init);
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for (int i = 0; i < GetSize(wirebits) && i < GetSize(initval); i++)
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{
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@ -78,22 +76,25 @@ struct ZinitPass : public Pass {
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continue;
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if (initbits.count(bit)) {
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if (initbits.at(bit) != val)
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if (initbits.at(bit).first != val)
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log_error("Conflicting init values for signal %s (%s = %s != %s).\n",
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log_signal(bit), log_signal(SigBit(wire, i)),
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log_signal(val), log_signal(initbits.at(bit)));
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log_signal(val), log_signal(initbits.at(bit).first));
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continue;
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}
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initbits[bit] = val;
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initbits[bit] = std::make_pair(val,SigBit(wire,i));
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}
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}
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pool<IdString> dff_types = {
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ID($ff), ID($dff), ID($dffe), ID($dffsr), ID($adff),
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// FIXME: It would appear that supporting
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// $dffsr/$_DFFSR_* would require a new
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// cell type where S has priority over R
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ID($ff), ID($dff), ID($dffe), /*ID($dffsr),*/ ID($adff),
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ID($_FF_), ID($_DFFE_NN_), ID($_DFFE_NP_), ID($_DFFE_PN_), ID($_DFFE_PP_),
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ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
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ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_),
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/*ID($_DFFSR_NNN_), ID($_DFFSR_NNP_), ID($_DFFSR_NPN_), ID($_DFFSR_NPP_),
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ID($_DFFSR_PNN_), ID($_DFFSR_PNP_), ID($_DFFSR_PPN_), ID($_DFFSR_PPP_),*/
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ID($_DFF_N_), ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
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ID($_DFF_P_), ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)
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};
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@ -113,8 +114,10 @@ struct ZinitPass : public Pass {
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for (int i = 0; i < GetSize(sig_q); i++) {
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if (initbits.count(sig_q[i])) {
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initval.bits.push_back(initbits.at(sig_q[i]));
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donebits.insert(sig_q[i]);
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const auto &d = initbits.at(sig_q[i]);
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initval.bits.push_back(d.first);
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const auto &b = d.second;
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b.wire->attributes.at(ID::init)[b.offset] = State::Sx;
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} else
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initval.bits.push_back(all_mode ? State::S0 : State::Sx);
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}
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@ -123,11 +126,11 @@ struct ZinitPass : public Pass {
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initwire->attributes[ID::init] = initval;
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for (int i = 0; i < GetSize(initwire); i++)
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if (initval.bits.at(i) == State::S1)
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if (initval[i] == State::S1)
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{
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sig_d[i] = module->NotGate(NEW_ID, sig_d[i]);
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module->addNotGate(NEW_ID, SigSpec(initwire, i), sig_q[i]);
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initwire->attributes[ID::init].bits.at(i) = State::S0;
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initwire->attributes[ID::init][i] = State::S0;
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}
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else
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{
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@ -139,11 +142,24 @@ struct ZinitPass : public Pass {
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cell->setPort(ID::D, sig_d);
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cell->setPort(ID::Q, initwire);
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}
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for (auto &it : initbits)
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if (donebits.count(it.first) == 0)
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log_error("Failed to handle init bit %s = %s.\n", log_signal(it.first), log_signal(it.second));
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if (cell->type == ID($adff)) {
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auto val = cell->getParam(ID::ARST_VALUE);
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for (int i = 0; i < GetSize(initwire); i++)
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if (initval[i] == State::S1)
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val[i] = (val[i] == State::S1 ? State::S0 : State::S1);
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cell->setParam(ID::ARST_VALUE, std::move(val));
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}
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else if (cell->type.in(ID($_DFF_NN0_), ID($_DFF_NN1_), ID($_DFF_NP0_), ID($_DFF_NP1_),
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ID($_DFF_PN0_), ID($_DFF_PN1_), ID($_DFF_PP0_), ID($_DFF_PP1_)))
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{
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if (initval == State::S1) {
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std::string t = cell->type.str();
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t[8] = (t[8] == '0' ? '1' : '0');
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cell->type = t;
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}
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}
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}
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}
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}
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} ZinitPass;
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@ -0,0 +1,57 @@
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read_verilog -icells <<EOT
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module top(input C, R, input [1:0] D, (* init = {2'b10, 2'b01, 1'b1, {8{1'b1}}} *) output [12:0] Q);
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(* init = 1'b1 *)
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wire unused;
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$_DFF_NN0_ dff0 (.C(C), .D(D[0]), .R(R), .Q(Q[0]));
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$_DFF_NN1_ dff1 (.C(C), .D(D[0]), .R(R), .Q(Q[1]));
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$_DFF_NP0_ dff2 (.C(C), .D(D[0]), .R(R), .Q(Q[2]));
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$_DFF_NP1_ dff3 (.C(C), .D(D[0]), .R(R), .Q(Q[3]));
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$_DFF_PN0_ dff4 (.C(C), .D(D[0]), .R(R), .Q(Q[4]));
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$_DFF_PN1_ dff5 (.C(C), .D(D[0]), .R(R), .Q(Q[5]));
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$_DFF_PP0_ dff6 (.C(C), .D(D[0]), .R(R), .Q(Q[6]));
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$_DFF_PP1_ dff7 (.C(C), .D(D[0]), .R(R), .Q(Q[7]));
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$adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) dff8 (.CLK(C), .ARST(R), .D(D), .Q(Q[10:9]));
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$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11]));
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endmodule
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EOT
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equiv_opt -assert -map +/simcells.v -multiclock zinit
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design -load postopt
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select -assert-count 20 t:$_NOT_
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select -assert-count 1 w:unused a:init %i
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select -assert-count 1 w:Q a:init=13'bxxxx1xxxxxxxx %i
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select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFF_??1_ %i
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select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$_DFF_??0_ %i
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design -reset
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read_verilog -icells <<EOT
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module top(input C, R, input [1:0] D, (* init = {2'bx0, 2'b0x, 1'b1, {8{1'b0}}} *) output [12:0] Q);
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(* init = 1'b1 *)
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wire unused;
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$_DFF_NN0_ dff0 (.C(C), .D(D[0]), .R(R), .Q(Q[0]));
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$_DFF_NN1_ dff1 (.C(C), .D(D[0]), .R(R), .Q(Q[1]));
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$_DFF_NP0_ dff2 (.C(C), .D(D[0]), .R(R), .Q(Q[2]));
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$_DFF_NP1_ dff3 (.C(C), .D(D[0]), .R(R), .Q(Q[3]));
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$_DFF_PN0_ dff4 (.C(C), .D(D[0]), .R(R), .Q(Q[4]));
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$_DFF_PN1_ dff5 (.C(C), .D(D[0]), .R(R), .Q(Q[5]));
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$_DFF_PP0_ dff6 (.C(C), .D(D[0]), .R(R), .Q(Q[6]));
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$_DFF_PP1_ dff7 (.C(C), .D(D[0]), .R(R), .Q(Q[7]));
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$adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) dff8 (.CLK(C), .ARST(R), .D(D), .Q(Q[10:9]));
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$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11]));
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endmodule
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EOT
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equiv_opt -assert -map +/simcells.v -multiclock zinit
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design -load postopt
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select -assert-count 0 t:$_NOT_
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select -assert-count 1 w:unused a:init %i
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select -assert-count 1 w:Q a:init=13'bxxxx1xxxxxxxx %i
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select -assert-count 4 c:dff0 c:dff2 c:dff4 c:dff6 %% t:$_DFF_??0_ %i
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select -assert-count 4 c:dff1 c:dff3 c:dff5 c:dff7 %% t:$_DFF_??1_ %i
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