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2,177 Commits 75 Branches 48 Tags 61 MiB
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2177 Commits

Author SHA1 Message Date
Clifford Wolf 554a8df5e2 Added "proc_dlatch" 2015-02-12 16:56:01 +01:00
Clifford Wolf 87819c62fa Less aggressive "share" defaults 2015-02-10 20:51:37 +01:00
Clifford Wolf 4f68a77e3f Improved read_verilog support for empty behavioral statements 2015-02-10 12:17:29 +01:00
Clifford Wolf 510deb3577 Added "scc -expect <N> -nofeedback" 2015-02-10 08:48:55 +01:00
Clifford Wolf adf4ecbc1f Some hashlib improvements 2015-02-09 20:11:51 +01:00
Clifford Wolf 68979d1395 Various changes to release checklist 2015-02-09 16:36:37 +01:00
Clifford Wolf a779a09771 Fixed creation of command reference in manual 2015-02-09 13:24:29 +01:00
Clifford Wolf e0ff4d1152 We are now in 0.5+ development 2015-02-09 13:13:51 +01:00
Clifford Wolf c3c9fbfb8c Yosys 0.5 2015-02-09 12:49:52 +01:00
Clifford Wolf 8901f405ca Bugfix in "make vcxsrc" 2015-02-09 12:48:15 +01:00
Clifford Wolf b944fef925 Updated command reference in manual 2015-02-09 12:05:02 +01:00
Clifford Wolf 85887de547 Various presentation fixes 2015-02-09 12:02:21 +01:00
Clifford Wolf f889e3d385 Fixed iterator invalidation bug in "rename" command 2015-02-09 00:18:36 +01:00
Clifford Wolf 139648554d CodingReadme update 2015-02-08 23:30:15 +01:00
Clifford Wolf 07afb14318 Fixed bug in "show -format .." 2015-02-08 23:29:54 +01:00
Clifford Wolf 183d4f8e71 Added new APIs to changelog 2015-02-08 21:14:52 +01:00
Clifford Wolf bcd8a2fc56 Fixed eval_select_op() api 2015-02-08 19:06:16 +01:00
Clifford Wolf 09ee65a050 Added eval_select_args() and eval_select_op() 2015-02-08 18:56:06 +01:00
Clifford Wolf 0fcc8c1467 Minor "make vgtest" changes 2015-02-08 15:13:51 +01:00
Clifford Wolf 6d2f31c04a Various ModIndex improvements 2015-02-08 14:23:12 +01:00
Clifford Wolf b10f0088d1 Added Yosys 0.5 Changelog 2015-02-08 12:03:51 +01:00
Clifford Wolf c3ce824af0 Various updates to CodingReadme 2015-02-08 12:03:51 +01:00
Clifford Wolf 5170b86108 Added equiv_add 2015-02-08 11:59:38 +01:00
Clifford Wolf 234a45a3d5 Ignore explicit assignments to constants in HDL code 2015-02-08 00:58:03 +01:00
Clifford Wolf c8305e3a6d Fixed a bug with autowire bit size 
(removed leftover from when we tried to auto-size the wires)
 2015-02-08 00:48:23 +01:00
Clifford Wolf fbb16712f1 fixed typo 2015-02-08 00:16:59 +01:00
Clifford Wolf bbfc1bd7cf Added "yosys-config --build modname.so cppsources.." 2015-02-08 00:14:07 +01:00
Clifford Wolf 05d4223fb6 Added SigSpec::has_const() 2015-02-08 00:01:51 +01:00
Clifford Wolf 0da320f151 Cleanup in add_share_file make macro 2015-02-08 00:01:31 +01:00
Clifford Wolf 2ef812d67e Removed "make mklibyosys" 2015-02-07 19:05:06 +01:00
Clifford Wolf 743da01e9e Improved building of plugins 2015-02-07 19:04:06 +01:00
Clifford Wolf cc400b279a Added "make uninstall" 2015-02-07 17:46:46 +01:00
Clifford Wolf dce1fae777 Added cell->known(), cell->input(portname), cell->output(portname) 2015-02-07 11:40:19 +01:00
Clifford Wolf d5e30978e9 Added "select -read" 2015-02-06 10:01:22 +01:00
Clifford Wolf ac7d5e0658 Auto-detect TCL version 2015-02-05 23:39:26 +01:00
Clifford Wolf a038787c9b Added onehot attribute 2015-02-04 18:52:54 +01:00
Clifford Wolf 8805c24640 Fixed opt_clean performance bug 2015-02-04 16:34:06 +01:00
Clifford Wolf 853e949c0e Disabled (unused) Xilinx tristate buffers 2015-02-04 16:33:59 +01:00
Clifford Wolf a8f4a099b5 Using design->selected_modules() in opt_* 2015-02-03 23:45:01 +01:00
Clifford Wolf 5b41470e15 Skip blackbox modules in design->selected_modules() 2015-02-03 23:12:23 +01:00
Clifford Wolf 8514fe79db Added "yosys -L logfile" 2015-02-03 23:12:23 +01:00
Clifford Wolf 30ec64656b Merge branch 'master' of github.com:cliffordwolf/yosys 2015-02-01 23:07:00 +01:00
Clifford Wolf bebbf2e5a4 no support for 6-series xilinx devices 2015-02-01 23:06:44 +01:00
Clifford Wolf 6eb34038f4 Merge pull request #48 from rubund/master 
Fixed typos found by lintian
 2015-02-01 22:55:52 +01:00
Clifford Wolf 893fe87a33 Improved performance in equiv_simple 2015-02-01 22:50:48 +01:00
Ruben Undheim 49649d6ef0 Fixed typos found by lintian 2015-02-01 21:49:55 +01:00
Clifford Wolf 3cbfa3815e Removed old XST-based xilinx examples 2015-02-01 17:10:46 +01:00
Clifford Wolf 816fe6bbe0 Added Xilinx example for Basys3 board 2015-02-01 17:09:34 +01:00
Clifford Wolf 6978f3a77b Added EDIF backend support for multi-bit cell ports 2015-02-01 15:43:35 +01:00
Clifford Wolf 1b159bc955 Added missing ports and parameters to xilinx brams 2015-02-01 15:42:59 +01:00