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yosys
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3420 Commits

Author SHA1 Message Date
Clifford Wolf c17d98f55c Removed shebang line from smtio.py, fixes #279 2016-11-27 12:11:04 +01:00
Clifford Wolf 5c2c78e2dd Added wire start_offset and upto handling BLIF back-end 2016-11-23 13:54:33 +01:00
Clifford Wolf e444e59963 Added wire start_offset and upto handling to splitnets cmd 2016-11-23 13:54:33 +01:00
Clifford Wolf 73653de5ff Merge pull request #274 from oldtopman/lcurses 
Added optional flag for linking curses with readline.
 2016-11-22 21:24:45 +01:00
Clifford Wolf f257ccf22e Added "yosys-smtbmc --append" 2016-11-22 21:21:13 +01:00
oldtopman 277f478572 Added optional flag for linking curses with readline. 2016-11-21 23:11:58 -07:00
Clifford Wolf 3b73d3f140 Merge pull request #272 from AlexDaniel/master 
Markdownify README (№2)
 2016-11-19 23:25:58 +01:00
Aleks-Daniel Jakimenko-Aleksejev 3c86da8000
Keep lines under 80 characters 
Recent README changes added some characters to existing lines, which
made them longer than 80 characters. This commit fixes that.
 2016-11-19 20:51:50 +02:00
Clifford Wolf 55785a96eb Improved ABC default scripts 2016-11-19 18:20:54 +01:00
Aleks-Daniel Jakimenko-Aleksejev 751ad3c618
Markdownify README even further 2016-11-19 19:07:02 +02:00
Clifford Wolf 487b19b4fa Merge pull request #271 from azidar/bugfix-assign-wmask 
Bugfix: include assign to write-mask
 2016-11-19 17:36:07 +01:00
Adam Izraelevitz f77dc3bacc Bugfix: include assign to write-mask 2016-11-18 11:49:26 -08:00
Clifford Wolf e01382739d More progress in FIRRTL back-end 2016-11-18 02:41:29 +01:00
Clifford Wolf c051115e03 Progress in FIRRTL back-end 2016-11-18 00:32:35 +01:00
Clifford Wolf 57966a619f Added first draft of FIRRTL back-end 2016-11-17 23:36:47 +01:00
Clifford Wolf ce132cf652 Cleanups and fixed in write_verilog regarding reg init 2016-11-16 12:00:39 +01:00
Clifford Wolf 70d7a02cae Added support for hierarchical defparams 2016-11-15 13:35:19 +01:00
Clifford Wolf a926a6afc2 Remember global declarations and defines accross read_verilog calls 2016-11-15 12:42:43 +01:00
Clifford Wolf a2206180d6 Merge pull request #268 from AlexDaniel/master 
Markdownify README
 2016-11-13 21:47:51 +01:00
Aleks-Daniel Jakimenko-Aleksejev d4e1592609
Markdownify README 
This is the first commit in series. There are many other things that
could be improved, this is just the first renderable version.
 2016-11-12 23:33:28 +02:00
Clifford Wolf 1827a48964 Minor bugfix in submod 2016-11-09 13:13:26 +01:00
Clifford Wolf 617693e691 Progress in examples/gowin/ 2016-11-08 19:07:22 +01:00
Clifford Wolf e9d73d2ee0 Indenting fixes in gowin sim cell lib 2016-11-08 18:54:00 +01:00
Clifford Wolf 97ac77513f Bugfix in "setundef" pass 2016-11-08 18:53:36 +01:00
Clifford Wolf 84badc97b3 Added examples/gowin/ 2016-11-07 12:55:56 +01:00
Clifford Wolf ef603c6fe1 Implemented "scc -set_attr" 2016-11-06 00:04:10 +01:00
Clifford Wolf 914aa8a5d3 Bugfix in "scc" command 2016-11-06 00:03:35 +01:00
Clifford Wolf 2874914bcb Fixed anonymous genblock object names 2016-11-04 07:46:30 +01:00
Clifford Wolf 3db2ac4e00 Added hex constant support to write_verilog 2016-11-03 12:13:23 +01:00
Clifford Wolf e3330fb98f We are now in 0.7+ development 2016-11-03 10:31:51 +01:00
Clifford Wolf 61f6811627 Yosys 0.7 2016-11-03 09:08:43 +01:00
Clifford Wolf 308a4b4a1b Bugfix in "hierarchy -check" 2016-11-02 20:09:57 +01:00
Clifford Wolf 4832faf5e9 Updated command reference in manual 2016-11-02 19:25:28 +01:00
Clifford Wolf 8e48685706 Changelog for Yosys 0.7 2016-11-02 18:53:30 +01:00
Clifford Wolf b63cace90f Added support for fsm_encoding="user" 2016-11-02 13:15:49 +01:00
Clifford Wolf 0c8e973d32 Added "fsm_expand -full" 2016-11-02 09:31:39 +01:00
Clifford Wolf 56e2bb88ae Some fixes in handling of signed arrays 2016-11-01 23:17:43 +01:00
Clifford Wolf 81bdf0ad0f iCE40 flow is not experimental anymore 2016-11-01 11:32:02 +01:00
Clifford Wolf cae5131bac Added initial version of "synth_gowin" 2016-11-01 11:31:13 +01:00
Clifford Wolf caa2fc62ef Adde "write_verilog -renameprefix -v" 2016-11-01 11:30:27 +01:00
Clifford Wolf 1e3c2bff72 Added support for (single-clock) transparent memories to bram tests 2016-11-01 10:03:13 +01:00
Clifford Wolf d9d38eeedb Bugfix in fsm_map for FSMs without reset state 2016-10-25 23:21:37 +02:00
Clifford Wolf aa72262330 Added avail params to ilang format, check module params in 'hierarchy -check' 2016-10-22 11:05:49 +02:00
Clifford Wolf 3655d7fea7 Added "setparam -type" 2016-10-19 13:54:04 +02:00
Clifford Wolf 042b67f024 No limit for length of lines in BLIF front-end 2016-10-19 12:44:58 +02:00
Clifford Wolf 0b3885bbfd Merge pull request #250 from azonenberg/master 
Add support for more GreenPak cells (edge detector, delay, pattern generator)
 2016-10-19 11:37:04 +02:00
Andrew Zonenberg 1cca1563c6 Fixed typo in last commit 2016-10-18 20:46:49 -07:00
Andrew Zonenberg e78fa157a3 greenpak4: Added GP_PGEN cell definition 2016-10-18 20:42:44 -07:00
Andrew Zonenberg 091d32b563 Added GLITCH_FILTER parameter to GP_DELAY 2016-10-18 19:53:19 -07:00
Andrew Zonenberg a818472f0c greenpak4: added model for GP_EDGEDET block 2016-10-18 19:33:26 -07:00