mirror of https://github.com/YosysHQ/yosys.git
Markdownify README
This is the first commit in series. There are many other things that could be improved, this is just the first renderable version.
This commit is contained in:
Aleks-Daniel Jakimenko-Aleksejev
parent
1827a48964
commit
d4e1592609
|
|
@ -1,26 +1,23 @@
|
|||
|
||||
/-----------------------------------------------------------------------------\
|
||||
| |
|
||||
| yosys -- Yosys Open SYnthesis Suite |
|
||||
| |
|
||||
| Copyright (C) 2012 - 2016 Clifford Wolf <clifford@clifford.at> |
|
||||
| |
|
||||
| Permission to use, copy, modify, and/or distribute this software for any |
|
||||
| purpose with or without fee is hereby granted, provided that the above |
|
||||
| copyright notice and this permission notice appear in all copies. |
|
||||
| |
|
||||
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
|
||||
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
|
||||
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
|
||||
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
|
||||
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
|
||||
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
|
||||
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
|
||||
| |
|
||||
\-----------------------------------------------------------------------------/
|
||||
|
||||
|
||||
```
|
||||
yosys -- Yosys Open SYnthesis Suite
|
||||
|
||||
Copyright (C) 2012 - 2016 Clifford Wolf <clifford@clifford.at>
|
||||
|
||||
Permission to use, copy, modify, and/or distribute this software for any
|
||||
purpose with or without fee is hereby granted, provided that the above
|
||||
copyright notice and this permission notice appear in all copies.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
```
|
||||
|
||||
|
||||
yosys – Yosys Open SYnthesis Suite
|
||||
===================================
|
||||
|
||||
This is a framework for RTL synthesis tools. It currently has
|
||||
|
|
@ -41,8 +38,7 @@ Web Site
|
|||
========
|
||||
|
||||
More information and documentation can be found on the Yosys web site:
|
||||
|
||||
http://www.clifford.at/yosys/
|
||||
http://www.clifford.at/yosys/
|
||||
|
||||
|
||||
Getting Started
|
||||
|
|
@ -61,9 +57,7 @@ prerequisites for building yosys:
|
|||
|
||||
There are also pre-compiled Yosys binary packages for Ubuntu and Win32 as well
|
||||
as a source distribution for Visual Studio. Visit the Yosys download page for
|
||||
more information:
|
||||
|
||||
http://www.clifford.at/yosys/download.html
|
||||
more information: http://www.clifford.at/yosys/download.html
|
||||
|
||||
To configure the build system to use a specific compiler, use one of
|
||||
|
||||
|
|
@ -74,7 +68,7 @@ For other compilers and build configurations it might be
|
|||
necessary to make some changes to the config section of the
|
||||
Makefile.
|
||||
|
||||
$ vi Makefile ..or..
|
||||
$ vi Makefile # ..or..
|
||||
$ vi Makefile.conf
|
||||
|
||||
To build Yosys simply type 'make' in this directory.
|
||||
|
|
@ -195,8 +189,8 @@ you can use the file examples/cmos/cmos_cells.lib from the yosys sources.
|
|||
Liberty file downloads for and information about free and open ASIC standard
|
||||
cell libraries can be found here:
|
||||
|
||||
http://www.vlsitechnology.org/html/libraries.html
|
||||
http://www.vlsitechnology.org/synopsys/vsclib013.lib
|
||||
- http://www.vlsitechnology.org/html/libraries.html
|
||||
- http://www.vlsitechnology.org/synopsys/vsclib013.lib
|
||||
|
||||
The command "synth" provides a good default synthesis script (see "help synth").
|
||||
If possible a synthesis script should borrow from "synth". For example:
|
||||
|
|
@ -243,7 +237,7 @@ Verilog Attributes and non-standard features
|
|||
(also the non-standard "// synopsys parallel_case" directive)
|
||||
|
||||
- The "// synopsys translate_off" and "// synopsys translate_on"
|
||||
directives are also supported (but the use of `ifdef .. `endif
|
||||
directives are also supported (but the use of ``` `ifdef .. `endif ```
|
||||
is strongly recommended instead).
|
||||
|
||||
- The "nomem2reg" attribute on modules or arrays prohibits the
|
||||
|
|
@ -303,10 +297,10 @@ Verilog Attributes and non-standard features
|
|||
through the synthesis. When entities are combined, a new |-separated
|
||||
string is created that contains all the string from the original entities.
|
||||
|
||||
- In addition to the (* ... *) attribute syntax, yosys supports
|
||||
the non-standard {* ... *} attribute syntax to set default attributes
|
||||
for everything that comes after the {* ... *} statement. (Reset
|
||||
by adding an empty {* *} statement.)
|
||||
- In addition to the ``(* ... *)`` attribute syntax, yosys supports
|
||||
the non-standard ``{* ... *}`` attribute syntax to set default attributes
|
||||
for everything that comes after the ``{* ... *}`` statement. (Reset
|
||||
by adding an empty ``{* *}`` statement.)
|
||||
|
||||
- In module parameter and port declarations, and cell port and parameter
|
||||
lists, a trailing comma is ignored. This simplifies writing verilog code
|
||||
|
|
@ -448,4 +442,3 @@ Notes:
|
|||
- To run `make manual` you need to have installed yosys with `make install`,
|
||||
otherwise it will fail on finding `kernel/yosys.h` while building
|
||||
`PRESENTATION_Prog`.
|
||||
|
||||
Loading…
Reference in New Issue