riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
9,513 Commits 76 Branches 48 Tags 62 MiB
Commit Graph

845 Commits

Author SHA1 Message Date
Eddie Hung 95763c8d18 abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes 2020-05-14 10:33:56 -07:00
Eddie Hung e6b55e8b38 synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad 2020-05-04 11:44:00 -07:00
Eddie Hung d2d90e4504 xilinx: improve xilinx_dffopt message 2020-04-22 16:25:23 -07:00
Marcelina Kościelnicka b4d76309e1 Use default parameter value in getParam 
Fixes #1822.
 2020-04-21 19:09:00 +02:00
Marcelina Kościelnicka 38a0c30d65 Get rid of dffsr2dff. 
This pass is a proper subset of opt_rmdff, which is called by opt, which
is called by every synth flow in the coarse part.  Thus, it never
actually does anything and can be safely removed.
 2020-04-15 16:22:37 +02:00
Eddie Hung d61a6b81fc
Merge pull request #1648 from YosysHQ/eddie/cmp2lcu 
"techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
 2020-04-03 16:28:25 -07:00
Eddie Hung 051aefc3c2 synth_xilinx: techmap +/cmp2lut.v and +/cmp2lcu.v in 'coarse' 2020-04-03 14:28:22 -07:00
Eddie Hung 956ecd48f7 kernel: big fat patch to use more ID::*, otherwise ID(*) 2020-04-02 09:51:32 -07:00
Marcin Kościelnicki 9b982e929c xilinx: Mark IOBUFDS.IOB as external pad 2020-03-20 14:37:38 +01:00
Eddie Hung 7b543fdb0c xilinx: consider DSP48E1.ADREG 2020-03-04 12:04:02 -08:00
Eddie Hung 512596760b xilinx: cleanup DSP48E1 handling for abc9 2020-03-04 11:31:12 -08:00
Eddie Hung f65fc845e5 xilinx: improve specify for DSP48E1 2020-03-04 11:31:12 -08:00
Eddie Hung 78d4fff69d xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v 2020-03-04 11:31:12 -08:00
Eddie Hung 090e54569a Remove RAMB{18,36}E1 from cells_xtra.py 2020-02-27 10:33:04 -08:00
Eddie Hung 376319dc8d xilinx: Update RAMB* specify entries 2020-02-27 10:17:29 -08:00
Eddie Hung 3b74e0fa45 xilinx: add delays to INV 2020-02-27 10:17:29 -08:00
Eddie Hung b0ffd9cd8b Make +/xilinx/cells_sim.v legal 2020-02-27 10:17:29 -08:00
Eddie Hung 1ef1ca812b Get rid of (* abc9_{arrival,required} *) entirely 2020-02-27 10:17:29 -08:00
Eddie Hung 3ea5506f81 abc9_ops: use TimingInfo for -prep_{lut,box} too 2020-02-27 10:17:29 -08:00
Eddie Hung 7d86aceee3 Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy 2020-02-27 10:17:29 -08:00
Eddie Hung aac309626b Fix tests by gating some specify constructs from iverilog 2020-02-27 10:17:29 -08:00
Eddie Hung e22fee6cdd abc9_ops: ignore (* abc9_flop *) if not '-dff' 2020-02-27 10:17:29 -08:00
Eddie Hung 8408c13405 Update xilinx for ABC9 2020-02-27 10:17:29 -08:00
Eddie Hung ccc84f8923 Fix commented out specify statement 2020-02-27 10:17:29 -08:00
Eddie Hung 12d70ca8fb xilinx: improve specify functionality 2020-02-27 10:17:29 -08:00
Eddie Hung 577545488a xilinx: use specify blocks in place of abc9_{arrival,required} 2020-02-27 10:17:29 -08:00
Eddie Hung 0e7c55e2a7 Auto-generate .box/.lut files from specify blocks 2020-02-27 10:17:29 -08:00
Eddie Hung 74f49b1f55 abc9_ops: -prep_box, to be called once 2020-02-27 10:17:29 -08:00
Eddie Hung 5643c1b8c5 abc9_ops: -prep_lut and -write_lut to auto-generate LUT library 2020-02-27 10:17:29 -08:00
Piotr Binkowski 62ab100c61 xilinx: mark IOBUFDSE3 IOB pin as external 2020-02-27 13:15:57 +01:00
Eddie Hung 00d41905df abc9: deprecate abc9_ff.init wire for (* abc9_init *) attr 2020-02-13 12:33:58 -08:00
Eddie Hung c244b27b6d abc9: cleanup 2020-02-10 10:17:23 -08:00
Eddie Hung 2e8d6ec0b0 Remove unnecessary comma 2020-02-07 12:45:07 -08:00
Marcin Kościelnicki 89adef352f xilinx: Add support for LUT RAM on LUT4-based devices. 
There are multiple other kinds of RAMs supported on these devices, but
RAM16X1D is the only dual-port one.

Fixes #1549
 2020-02-07 09:03:22 +01:00
Marcin Kościelnicki d48950d92d xilinx: Initial support for LUT4 devices. 
Adds support for mapping logic, including LUTs, wide LUTs, and carry
chains.

Fixes #1547
 2020-02-07 09:03:22 +01:00
Marcin Kościelnicki 30854b9c7f xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*. 2020-02-07 01:00:29 +01:00
Marcin Kościelnicki 95c46ccc55 xilinx: Add support for Spartan 3A DSP block RAMs. 
Part of #1550
 2020-02-07 01:00:29 +01:00
Eddie Hung d625e399cb Fix $lcu -> MUXCY mapping, credit @mwkmwkmwk 2020-02-06 11:25:07 -08:00
Eddie Hung 5ecbc6c7b2 Fix/cleanup +/xilinx/arith_map.v 2020-02-06 11:00:04 -08:00
Eddie Hung 0671ae7d79
Merge pull request #1661 from YosysHQ/eddie/abc9_required 
abc9: add support for required times
 2020-02-05 18:59:40 +01:00
Marcelina Kościelnicka 34d2fbd2f9
Add opt_lut_ins pass. (#1673) 2020-02-03 14:57:17 +01:00
Marcin Kościelnicki b44d0e041f xilinx: use RAM32M/RAM64M for memories with two read ports 
This fixes inefficient LUT RAM usage for memories with one write
and two read ports (commonly used as register files).
 2020-02-02 14:34:21 +01:00
Eddie Hung c5971cb16c synth_xilinx: cleanup help 2020-01-28 17:48:43 -08:00
Eddie Hung 0fd64aab25 synth_xilinx: fix help when no active_design; fixes #1664 2020-01-28 17:41:57 -08:00
Marcin Kościelnicki 7e0e42f907 xilinx: Add simulation model for DSP48 (Virtex 4). 2020-01-29 01:40:00 +01:00
Eddie Hung 7939727d14
Merge pull request #1660 from YosysHQ/eddie/abc9_unpermute_luts 
Unpermute LUT ordering for ice40/ecp5/xilinx
 2020-01-28 11:55:51 -08:00
Eddie Hung 245b8c4ab6 Fix unresolved conflict from #1573 2020-01-28 10:17:47 -08:00
N. Engelhardt 086c133ea5
Merge pull request #1573 from YosysHQ/eddie/xilinx_tristate 
synth_xilinx: error out if tristate without '-iopad'
 2020-01-28 17:24:54 +01:00
Eddie Hung ce6a690d27 xilinx/ice40/ecp5: undo permuting LUT masks in lut_map 
Now done in read_aiger
 2020-01-27 13:30:27 -08:00
Eddie Hung f2576c096c Merge branch 'eddie/abc9_refactor' into eddie/abc9_required 2020-01-27 12:29:28 -08:00