whitequark
8c4cb1885b
Merge pull request #2182 from whitequark/update-abc
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Update ABC
2020-06-22 17:01:59 +00:00
whitequark
778332384a
Update ABC.
2020-06-22 14:18:07 +00:00
whitequark
97f3a7fc30
Merge pull request #2181 from whitequark/minisat-wasm-signal
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minisat: add missing include guard for WASI
2020-06-22 00:10:25 +00:00
whitequark
21d44ebec7
minisat: add missing include guard for WASI.
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Including signal.h used to be allowed in WASI by mistake, but it's
an error since SDK 11.
2020-06-21 21:26:21 +00:00
whitequark
692ec5fc9d
Merge pull request #2180 from Xiretza/pyosys-override
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pyosys: Use C++11 override keyword for bindings
2020-06-21 15:19:23 +00:00
Xiretza
a367281d30
pyosys: Use C++11 override keyword for bindings
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7191dd16
dropped the YS_OVERRIDE macro, but it was still being generated
by the python bindings generator, resulting in errors like these when
compiled with ENABLE_PYOSYS=1:
kernel/python_wrappers.cc:350:21: error: expected ‘;’ at end of member declaration
350 | virtual void help() YS_OVERRIDE;
| ^
| ;
kernel/python_wrappers.cc:350:23: error: ‘YS_OVERRIDE’ does not name a type
350 | virtual void help() YS_OVERRIDE;
| ^~~~~~~~~~~
2020-06-21 16:30:00 +02:00
whitequark
992d694d39
Merge pull request #2177 from boqwxp/dict-iterator-jump
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hashlib, rtlil: Add `operator+()` and `operator+=()` to `dict` iterators
2020-06-21 02:05:12 +00:00
Alberto Gonzalez
d71a9badda
dict: Remove guard for past-the-end iterators that might mask problems in static analysis.
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Co-Authored-By: whitequark <whitequark@whitequark.org>
2020-06-19 21:04:29 +00:00
whitequark
338ecbe02f
Merge pull request #2178 from boqwxp/design-select
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rtlil: Add `Design::select()` for selecting whole modules
2020-06-19 19:57:25 +00:00
Alberto Gonzalez
3ccdab940c
rtlil: Add `Design::select()` for selecting whole modules.
2020-06-19 18:16:33 +00:00
Alberto Gonzalez
e5a2d17b5d
hashlib, rtlil: Add `operator+=()` to `dict<>::iterator` and `dict<>::const_iterator` and add `operator+()` and `operator+=()` to `ObjIterator`.
2020-06-19 17:44:29 +00:00
whitequark
d5d0cc88d2
Merge pull request #2175 from Xiretza/missing-noreturn
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Add missing [[noreturn]] to log_file_error()
2020-06-19 15:46:54 +00:00
Xiretza
817411044a
Add missing [[noreturn]] to log_file_error()
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Previously this was tagged only with YS_ATTRIBUTE(noreturn), but not
YS_NORETURN, so it got lost in #2173 , resulting in warnings in
frontends/ast/simplify.cc:
frontends/ast/simplify.cc:267:1: warning: function declared 'noreturn' should not return [-Winvalid-noreturn]
}
^
frontends/ast/simplify.cc:379:1: warning: function declared 'noreturn' should not return [-Winvalid-noreturn]
}
^
2020-06-19 11:46:06 +02:00
whitequark
ede4b10da8
Merge pull request #2173 from whitequark/use-cxx11-final-override
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Use C++11 final/override/[[noreturn]]
2020-06-19 06:15:33 +00:00
whitequark
bcbd44c673
Merge pull request #2174 from whitequark/fix-github-linguist
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Fix GitHub misidentifying *.v files as Coq
2020-06-19 06:09:42 +00:00
whitequark
78f39f6ebc
Fix GitHub misidentifying *.v files as Coq.
2020-06-19 06:08:18 +00:00
whitequark
87f45b7bd0
Merge pull request #2171 from whitequark/cxxrtl-accessors
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cxxrtl: add .get() and .set() accessors on value<> and wire<>
2020-06-19 03:52:29 +00:00
whitequark
962a2f3bff
cxxrtl: add .get() and .set() accessors on value<> and wire<>.
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For several reasons:
* They're more convenient than accessing .data.
* They accommodate variably-sized types like size_t transparently.
* They statically ensure that no out of range conversions happen.
For now these are only provided for unsigned integers, but eventually
they should be provided for signed integers too. (Annoyingly this
affects conversions to/from `char` at the moment.)
Fixes #2127 .
2020-06-19 02:31:35 +00:00
whitequark
b3b9f1bf2e
Merge pull request #2170 from boqwxp/cutpoint-efficiency
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cutpoint: Improve efficiency by iterating over module ports instead of module wires
2020-06-19 01:13:19 +00:00
whitequark
60478a8e3a
Use C++11 [[noreturn]] attribute.
2020-06-19 01:06:48 +00:00
whitequark
7191dd16f9
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
Alberto Gonzalez
76dfa81790
cutpoint: Improve efficiency by iterating over module ports instead of module wires.
2020-06-18 17:42:36 +00:00
N. Engelhardt
dfde1cf1c5
Merge pull request #2153 from boqwxp/splitnets-cleanup
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splitnets: Cleanup and efficiency improvements
2020-06-18 19:16:55 +02:00
whitequark
8344846787
Merge pull request #2167 from whitequark/cxxrtl-fix-ndebug
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cxxrtl: don't compute vital values in log_assert()
2020-06-18 16:57:51 +00:00
whitequark
5439faebf9
Merge pull request #2142 from whitequark/splitnets-hdlname
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splitnets: propagate (*hdlname*) and disambiguate via start_offset
2020-06-18 16:57:24 +00:00
Miodrag Milanović
2123019ac6
Merge pull request #2164 from madebr/msvc
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Get yosys building on Visual Studio
2020-06-18 12:44:21 +02:00
whitequark
3c4e974d7b
cxxrtl: don't compute vital values in log_assert().
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This breaks NDEBUG builds.
Fixes #2166 .
2020-06-17 19:27:47 +00:00
Anonymous Maarten
60fb9cabcf
msvc does not support designated initializers in structs
2020-06-17 16:20:52 +02:00
Anonymous Maarten
504f220619
MSVC does not understand __builtin_unreachable
2020-06-17 15:10:08 +02:00
Anonymous Maarten
35008e6d40
MSVC cannot omit operand in conditional
2020-06-17 15:10:08 +02:00
Anonymous Maarten
c9c13c29df
MSVC defines TRANSPARENT too
2020-06-17 15:10:08 +02:00
whitequark
c4f20f744b
Merge pull request #2163 from jfng/cxxrtl-blackbox-debuginfo
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cxxrtl: restrict the debug info of a blackbox to its ports.
2020-06-17 06:07:41 +00:00
whitequark
eaf66037a5
Merge pull request #2160 from whitequark/cxxrtl-fix-warning
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cxxrtl: avoid unused variable warning for transparent $memrd ports
2020-06-17 06:06:58 +00:00
Jean-François Nguyen
8d98c3861d
cxxrtl: restrict the debug info of a blackbox to its ports.
2020-06-16 15:30:56 +02:00
N. Engelhardt
39ba90a8b8
Merge pull request #2156 from XarkLabs/master
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Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH
2020-06-16 12:31:34 +02:00
whitequark
334ec5fa0a
Merge pull request #2159 from MerryMage/cxxrtl-mul
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cxxrtl: Implement chunk-wise multiplication
2020-06-15 06:08:17 +00:00
whitequark
8d70f7abf9
cxxrtl: avoid unused variable warning for transparent $memrd ports. NFC.
2020-06-15 06:00:16 +00:00
MerryMage
f7ae9b0851
cxxrtl: Implement chunk-wise multiplication
2020-06-15 05:54:57 +01:00
whitequark
9d0f1aa222
Merge pull request #2158 from miek/sshr-sign-extension
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cxxrtl: fix sshr sign-extension.
2020-06-15 01:37:05 +00:00
Mike Walters
66a2de2912
cxxrtl: fix sshr sign-extension.
2020-06-15 01:01:49 +01:00
Xark
9509444ef2
Fix Verilator sim warnings: 1 BLKSEQ and 3 WIDTH
2020-06-14 00:45:22 -07:00
whitequark
74e93e083f
Merge pull request #2155 from whitequark/fix-wasm-wasi-sdk-11
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kernel: guard include of signal.h more precisely
2020-06-13 23:28:18 +00:00
whitequark
7137f99658
kernel: guard include of signal.h more precisely.
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Upgrading to WASI SDK 11.0 caused the WASM build to fail because WASM
does not have signals. (Arguably Yosys was broken even before, it was
just broken silently.)
2020-06-13 22:37:04 +00:00
whitequark
971a765155
Merge pull request #2151 from whitequark/cxxrtl-fix-rzext
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cxxrtl: fix rzext()
2020-06-13 22:18:35 +00:00
Alberto Gonzalez
f5d7cd60f5
splitnets: Clean up pseudo-private member usage
2020-06-13 05:47:55 +00:00
Alberto Gonzalez
b70de98bd1
splitnets: Slightly improve efficiency by avoiding some unnecessary lookups
2020-06-13 05:26:30 +00:00
whitequark
dc6961f3d4
Merge pull request #2145 from whitequark/cxxrtl-splitnets
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cxxrtl: handle multipart signals
2020-06-13 04:23:22 +00:00
whitequark
3783ad625e
Merge pull request #2152 from whitequark/cxxrtl-always-inline
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cxxrtl: always inline internal cells and slice/concat operations
2020-06-13 04:17:49 +00:00
whitequark
107911dbec
cxxrtl: always inline internal cells and slice/concat operations.
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This can result in massive reduction in runtime, up to 50% depending
on workload. Currently people are using `-mllvm -inline-threshold=`
as a workaround (with clang++), but this solution is more portable.
2020-06-13 01:52:06 +00:00
whitequark
6cf02ed94f
cxxrtl: fix rzext().
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This was a correctness issue, but one of the consequences is that it
resulted in jumps in generated machine code where there should have
been none. As a side effect of fixing the bug, Minerva SoC became 10%
faster.
2020-06-13 00:49:44 +00:00