mirror of https://github.com/YosysHQ/yosys.git
cxxrtl: restrict the debug info of a blackbox to its ports.
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@ -1621,6 +1621,8 @@ struct CxxrtlWorker {
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for (auto wire : module->wires()) {
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if (wire->name[0] != '\\')
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continue;
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if (module->get_bool_attribute(ID(cxxrtl_blackbox)) && (wire->port_id == 0))
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continue;
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count_public_wires++;
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if (debug_const_wires.count(wire)) {
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// Wire tied to a constant
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@ -1647,19 +1649,21 @@ struct CxxrtlWorker {
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count_skipped_wires++;
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}
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}
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for (auto &memory_it : module->memories) {
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if (memory_it.first[0] != '\\')
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continue;
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f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
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f << ", debug_item(" << mangle(memory_it.second) << ", ";
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f << memory_it.second->start_offset << "));\n";
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}
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for (auto cell : module->cells()) {
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if (is_internal_cell(cell->type))
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continue;
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const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
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f << indent << mangle(cell) << access << "debug_info(items, ";
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f << "path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ");\n";
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if (!module->get_bool_attribute(ID(cxxrtl_blackbox))) {
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for (auto &memory_it : module->memories) {
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if (memory_it.first[0] != '\\')
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continue;
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f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
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f << ", debug_item(" << mangle(memory_it.second) << ", ";
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f << memory_it.second->start_offset << "));\n";
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}
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for (auto cell : module->cells()) {
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if (is_internal_cell(cell->type))
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continue;
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const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
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f << indent << mangle(cell) << access << "debug_info(items, ";
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f << "path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ");\n";
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}
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}
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dec_indent();
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