mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #2145 from whitequark/cxxrtl-splitnets
cxxrtl: handle multipart signals
This commit is contained in:
commit
dc6961f3d4
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@ -771,76 +771,119 @@ struct debug_item : ::cxxrtl_object {
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debug_item(const ::cxxrtl_object &object) : cxxrtl_object(object) {}
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template<size_t Bits>
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debug_item(value<Bits> &item) {
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debug_item(value<Bits> &item, size_t lsb_offset = 0) {
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static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
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"value<Bits> is not compatible with C layout");
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type = VALUE;
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width = Bits;
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depth = 1;
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curr = item.data;
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next = item.data;
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type = VALUE;
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width = Bits;
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lsb_at = lsb_offset;
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depth = 1;
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zero_at = 0;
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curr = item.data;
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next = item.data;
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}
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template<size_t Bits>
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debug_item(const value<Bits> &item) {
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debug_item(const value<Bits> &item, size_t lsb_offset = 0) {
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static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
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"value<Bits> is not compatible with C layout");
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type = VALUE;
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width = Bits;
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depth = 1;
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curr = const_cast<chunk_t*>(item.data);
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next = nullptr;
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type = VALUE;
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width = Bits;
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lsb_at = lsb_offset;
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depth = 1;
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zero_at = 0;
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curr = const_cast<chunk_t*>(item.data);
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next = nullptr;
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}
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template<size_t Bits>
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debug_item(wire<Bits> &item) {
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debug_item(wire<Bits> &item, size_t lsb_offset = 0) {
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static_assert(sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&
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sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t),
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"wire<Bits> is not compatible with C layout");
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type = WIRE;
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width = Bits;
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depth = 1;
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curr = item.curr.data;
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next = item.next.data;
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type = WIRE;
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width = Bits;
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lsb_at = lsb_offset;
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depth = 1;
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zero_at = 0;
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curr = item.curr.data;
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next = item.next.data;
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}
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template<size_t Width>
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debug_item(memory<Width> &item) {
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debug_item(memory<Width> &item, size_t zero_offset = 0) {
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static_assert(sizeof(item.data[0]) == value<Width>::chunks * sizeof(chunk_t),
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"memory<Width> is not compatible with C layout");
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type = MEMORY;
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width = Width;
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depth = item.data.size();
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curr = item.data.empty() ? nullptr : item.data[0].data;
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next = nullptr;
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type = MEMORY;
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width = Width;
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lsb_at = 0;
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depth = item.data.size();
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zero_at = zero_offset;
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curr = item.data.empty() ? nullptr : item.data[0].data;
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next = nullptr;
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}
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template<size_t Bits>
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debug_item(debug_alias, const value<Bits> &item) {
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debug_item(debug_alias, const value<Bits> &item, size_t lsb_offset = 0) {
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static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
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"value<Bits> is not compatible with C layout");
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type = ALIAS;
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width = Bits;
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depth = 1;
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curr = const_cast<chunk_t*>(item.data);
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next = nullptr;
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type = ALIAS;
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width = Bits;
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lsb_at = lsb_offset;
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depth = 1;
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zero_at = 0;
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curr = const_cast<chunk_t*>(item.data);
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next = nullptr;
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}
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template<size_t Bits>
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debug_item(debug_alias, const wire<Bits> &item) {
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debug_item(debug_alias, const wire<Bits> &item, size_t lsb_offset = 0) {
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static_assert(sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&
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sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t),
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"wire<Bits> is not compatible with C layout");
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type = ALIAS;
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width = Bits;
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depth = 1;
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curr = const_cast<chunk_t*>(item.curr.data);
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next = nullptr;
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type = ALIAS;
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width = Bits;
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lsb_at = lsb_offset;
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depth = 1;
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zero_at = 0;
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curr = const_cast<chunk_t*>(item.curr.data);
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next = nullptr;
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}
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};
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static_assert(std::is_standard_layout<debug_item>::value, "debug_item is not compatible with C layout");
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typedef std::map<std::string, debug_item> debug_items;
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struct debug_items {
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std::map<std::string, std::vector<debug_item>> table;
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void add(const std::string &name, debug_item &&item) {
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std::vector<debug_item> &parts = table[name];
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parts.emplace_back(item);
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std::sort(parts.begin(), parts.end(),
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[](const debug_item &a, const debug_item &b) {
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return a.lsb_at < b.lsb_at;
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});
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}
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size_t count(const std::string &name) const {
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if (table.count(name) == 0)
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return 0;
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return table.at(name).size();
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}
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const std::vector<debug_item> &parts_at(const std::string &name) const {
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return table.at(name);
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}
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const debug_item &at(const std::string &name) const {
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const std::vector<debug_item> &parts = table.at(name);
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assert(parts.size() == 1);
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return parts.at(0);
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}
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const debug_item &operator [](const std::string &name) const {
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return at(name);
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}
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};
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struct module {
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module() {}
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@ -1627,18 +1627,21 @@ struct CxxrtlWorker {
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f << indent << "static const value<" << wire->width << "> const_" << mangle(wire) << " = ";
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dump_const(debug_const_wires[wire]);
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f << ";\n";
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f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire));
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f << ", debug_item(const_" << mangle(wire) << "));\n";
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f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
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f << ", debug_item(const_" << mangle(wire) << ", ";
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f << wire->start_offset << "));\n";
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count_const_wires++;
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} else if (debug_alias_wires.count(wire)) {
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// Alias of a member wire
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f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire));
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f << ", debug_item(debug_alias(), " << mangle(debug_alias_wires[wire]) << "));\n";
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f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
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f << ", debug_item(debug_alias(), " << mangle(debug_alias_wires[wire]) << ", ";
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f << wire->start_offset << "));\n";
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count_alias_wires++;
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} else if (!localized_wires.count(wire)) {
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// Member wire
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f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire));
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f << ", debug_item(" << mangle(wire) << "));\n";
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f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(wire));
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f << ", debug_item(" << mangle(wire) << ", ";
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f << wire->start_offset << "));\n";
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count_member_wires++;
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} else {
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count_skipped_wires++;
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@ -1647,8 +1650,9 @@ struct CxxrtlWorker {
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for (auto &memory_it : module->memories) {
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if (memory_it.first[0] != '\\')
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continue;
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f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
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f << ", debug_item(" << mangle(memory_it.second) << "));\n";
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f << indent << "items.add(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
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f << ", debug_item(" << mangle(memory_it.second) << ", ";
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f << memory_it.second->start_offset << "));\n";
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}
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for (auto cell : module->cells()) {
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if (is_internal_cell(cell->type))
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@ -47,14 +47,17 @@ size_t cxxrtl_step(cxxrtl_handle handle) {
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return handle->module->step();
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}
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cxxrtl_object *cxxrtl_get(cxxrtl_handle handle, const char *name) {
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if (handle->objects.count(name) > 0)
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return static_cast<cxxrtl_object*>(&handle->objects.at(name));
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return nullptr;
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struct cxxrtl_object *cxxrtl_get_parts(cxxrtl_handle handle, const char *name, size_t *parts) {
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auto it = handle->objects.table.find(name);
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if (it == handle->objects.table.end())
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return nullptr;
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*parts = it->second.size();
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return static_cast<cxxrtl_object*>(&it->second[0]);
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}
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void cxxrtl_enum(cxxrtl_handle handle, void *data,
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void (*callback)(void *data, const char *name, cxxrtl_object *object)) {
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for (auto &it : handle->objects)
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callback(data, it.first.c_str(), static_cast<cxxrtl_object*>(&it.second));
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void (*callback)(void *data, const char *name,
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cxxrtl_object *object, size_t parts)) {
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for (auto &it : handle->objects.table)
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callback(data, it.first.c_str(), static_cast<cxxrtl_object*>(&it.second[0]), it.second.size());
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}
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@ -26,6 +26,7 @@
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#include <stddef.h>
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#include <stdint.h>
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#include <assert.h>
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#ifdef __cplusplus
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extern "C" {
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@ -113,9 +114,15 @@ struct cxxrtl_object {
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// Width of the object in bits.
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size_t width;
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// Index of the least significant bit.
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size_t lsb_at;
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// Depth of the object. Only meaningful for memories; for other objects, always 1.
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size_t depth;
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// Index of the first word. Only meaningful for memories; for other objects, always 0;
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size_t zero_at;
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// Bits stored in the object, as 32-bit chunks, least significant bits first.
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//
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// The width is rounded up to a multiple of 32; the padding bits are always set to 0 by
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@ -140,17 +147,36 @@ struct cxxrtl_object {
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// the top-level module instantiates a module `foo`, which in turn contains a wire `bar`, the full
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// hierarchical name is `\foo \bar`.
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//
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// Returns the object if it was found, NULL otherwise. The returned value is valid until the design
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// is destroyed.
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struct cxxrtl_object *cxxrtl_get(cxxrtl_handle handle, const char *name);
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// The storage of a single abstract object may be split (usually with the `splitnets` pass) into
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// many physical parts, all of which correspond to the same hierarchical name. To handle such cases,
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// this function returns an array and writes its length to `parts`. The array is sorted by `lsb_at`.
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//
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// Returns the object parts if it was found, NULL otherwise. The returned parts are valid until
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// the design is destroyed.
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struct cxxrtl_object *cxxrtl_get_parts(cxxrtl_handle handle, const char *name, size_t *parts);
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// Retrieve description of a single part simulated object.
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//
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// This function is a shortcut for the most common use of `cxxrtl_get_parts`. It asserts that,
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// if the object exists, it consists of a single part. If assertions are disabled, it returns NULL
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// for multi-part objects.
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inline struct cxxrtl_object *cxxrtl_get(cxxrtl_handle handle, const char *name) {
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size_t parts = 0;
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struct cxxrtl_object *object = cxxrtl_get_parts(handle, name, &parts);
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assert(object == NULL || parts == 1);
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if (object == NULL || parts == 1)
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return object;
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return NULL;
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}
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// Enumerate simulated objects.
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//
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// For every object in the simulation, `callback` is called with the provided `data`, the full
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// hierarchical name of the object (see `cxxrtl_get` for details), and the object description.
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// hierarchical name of the object (see `cxxrtl_get` for details), and the object parts.
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// The provided `name` and `object` values are valid until the design is destroyed.
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void cxxrtl_enum(cxxrtl_handle handle, void *data,
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void (*callback)(void *data, const char *name, struct cxxrtl_object *object));
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void (*callback)(void *data, const char *name,
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struct cxxrtl_object *object, size_t parts));
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#ifdef __cplusplus
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}
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@ -66,11 +66,19 @@ class vcd_writer {
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} while (ident != 0);
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}
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void emit_var(const variable &var, const std::string &type, const std::string &name) {
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void emit_var(const variable &var, const std::string &type, const std::string &name,
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size_t lsb_at, bool multipart) {
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assert(!streaming);
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buffer += "$var " + type + " " + std::to_string(var.width) + " ";
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emit_ident(var.ident);
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buffer += " " + name + " $end\n";
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buffer += " " + name;
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if (multipart || name.back() == ']' || lsb_at != 0) {
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if (var.width == 1)
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buffer += " [" + std::to_string(lsb_at) + "]";
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else
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buffer += " [" + std::to_string(lsb_at + var.width - 1) + ":" + std::to_string(lsb_at) + "]";
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}
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buffer += " $end\n";
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}
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void emit_enddefinitions() {
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@ -155,7 +163,7 @@ public:
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emit_timescale(number, unit);
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}
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void add(const std::string &hier_name, const debug_item &item) {
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void add(const std::string &hier_name, const debug_item &item, bool multipart = false) {
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std::vector<std::string> scope = split_hierarchy(hier_name);
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std::string name = scope.back();
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scope.pop_back();
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@ -164,17 +172,20 @@ public:
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switch (item.type) {
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// Not the best naming but oh well...
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case debug_item::VALUE:
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emit_var(register_variable(item.width, item.curr, /*constant=*/item.next == nullptr), "wire", name);
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emit_var(register_variable(item.width, item.curr, /*constant=*/item.next == nullptr),
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"wire", name, item.lsb_at, multipart);
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break;
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case debug_item::WIRE:
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emit_var(register_variable(item.width, item.curr), "reg", name);
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emit_var(register_variable(item.width, item.curr),
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"reg", name, item.lsb_at, multipart);
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break;
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case debug_item::MEMORY: {
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const size_t stride = (item.width + (sizeof(chunk_t) * 8 - 1)) / (sizeof(chunk_t) * 8);
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for (size_t index = 0; index < item.depth; index++) {
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chunk_t *nth_curr = &item.curr[stride * index];
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std::string nth_name = name + '[' + std::to_string(index) + ']';
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emit_var(register_variable(item.width, nth_curr), "reg", nth_name);
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emit_var(register_variable(item.width, nth_curr),
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"reg", nth_name, item.lsb_at, multipart);
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}
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break;
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}
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@ -183,7 +194,8 @@ public:
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// can actually change, and must be tracked. In most cases the VCD identifier will be
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// unified with the aliased reg, but we should handle the case where only the alias is
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// added to the VCD writer, too.
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emit_var(register_variable(item.width, item.curr), "wire", name);
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emit_var(register_variable(item.width, item.curr),
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"wire", name, item.lsb_at, multipart);
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break;
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}
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}
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@ -192,9 +204,10 @@ public:
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void add(const debug_items &items, const Filter &filter) {
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// `debug_items` is a map, so the items are already sorted in an order optimal for emitting
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// VCD scope sections.
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for (auto &it : items)
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if (filter(it.first, it.second))
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add(it.first, it.second);
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for (auto &it : items.table)
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for (auto &part : it.second)
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if (filter(it.first, part))
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add(it.first, part, it.second.size() > 1);
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}
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void add(const debug_items &items) {
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