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10585 Commits

Author SHA1 Message Date
William D. Jones 8b14152506 machxo2: Fix typos in FACADE_FF sim model. 2021-02-23 17:39:58 +01:00
William D. Jones 8348c45e4f machxo2: Fix naming of TRELLIS_IO ports to match PIO pins in routing graph. 2021-02-23 17:39:58 +01:00
William D. Jones 120404bfda machxo2: Improve help_mode output in synth_machxo2. 2021-02-23 17:39:58 +01:00
William D. Jones 3674eb34d4 machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires to IO cells. 2021-02-23 17:39:58 +01:00
William D. Jones 124780ecd9 machxo2: Add missing OSCH oscillator primitive. 2021-02-23 17:39:58 +01:00
William D. Jones c31b17a2e2 machxo2: Add believed-to-be-correct tribuf test. 2021-02-23 17:39:58 +01:00
William D. Jones c7aaa88f58 machxo2: Add passing fsm, mux, and shifter tests. 2021-02-23 17:39:58 +01:00
William D. Jones 453904dd00 machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives. 2021-02-23 17:39:58 +01:00
William D. Jones 597a54dbd0 machxo2: Add -noiopad option to synth_machxo2. 2021-02-23 17:39:58 +01:00
William D. Jones 3697f351d5 machxo2: Use correct INITVAL for LUT1 in FACADE_SLICE. 2021-02-23 17:39:58 +01:00
William D. Jones f07b8eb606 machxo2: Fix cells_sim typo where OFX1 was multiply-driven. 2021-02-23 17:39:58 +01:00
William D. Jones c76f361b56 machxo2: synth_machxo2 now maps ports to FACADE_IO. 2021-02-23 17:39:58 +01:00
William D. Jones 03cbf1327d machxo2: Add initial value for Q in FACADE_FF. 2021-02-23 17:39:58 +01:00
William D. Jones 0364ded385 machxo2: Add FACADE_IO simulation model. More comments on models. 2021-02-23 17:39:58 +01:00
William D. Jones 1b703d3f03 machxo2: Add FACADE_SLICE simulation model. 2021-02-23 17:39:58 +01:00
William D. Jones cc52eb53cd machxo2: Improve FACADE_FF simulation model. 2021-02-23 17:39:58 +01:00
William D. Jones 427fed23ee machxo2: Improve LUT4 techmap. Use same output port name for LUT4 as Lattice. 2021-02-23 17:39:58 +01:00
William D. Jones 19b043344c machxo2: Add dffe test. 2021-02-23 17:39:58 +01:00
William D. Jones 84937e9689 machxo2: Add dff.ys test, fix another cells_map.v typo. 2021-02-23 17:39:58 +01:00
William D. Jones 044393b990 machxo2: Fix more oversights in machxo2 models. logic.ys test passes. 2021-02-23 17:39:58 +01:00
William D. Jones 9cb0bae1b2 machxo2: Add test/arch/machxo2 directory (test does not pass). 2021-02-23 17:39:58 +01:00
William D. Jones b87f6a0906 machxo2: Fix typos. test/arch/run-test.sh passes. 2021-02-23 17:39:58 +01:00
William D. Jones 88c8f81260 machxo2: Create basic techlibs and synth_machxo2 pass. 2021-02-23 17:39:58 +01:00
Karol Gugala cc7d18d29a frontend: json: parse negative values 
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
 2021-02-23 00:26:11 +01:00
Marcelina Kościelnicka 4746ffd7b2 assertpmux: Fix crash on unused $pmux output. 
Fixes #2595.
 2021-02-22 23:30:28 +01:00
whitequark 01ccb80b70
Merge pull request #2586 from zachjs/tern-recurse 
verilog: support recursive functions using ternary expressions
 2021-02-21 20:56:04 +00:00
whitequark 3fee43cde0
Merge pull request #2591 from zachjs/verilog-preproc-unapplied 
verilog: error on macro invocations with missing argument lists
 2021-02-21 20:53:56 +00:00
Zachary Snow 220cb1f7bb verilog: error on macro invocations with missing argument lists 
This would previously complain about an undefined internal macro if the
unapplied macro had not already been used. If it had, it would
incorrectly use the arguments from the previous invocation.
 2021-02-19 09:18:41 -05:00
Yosys Bot 127484e675 Bump version 2021-02-18 00:10:06 +00:00
Claire Xen dbaccfbabe
Merge pull request #2590 from RobertBaruch/fix_fast_sop_mode 
Fixes command line for abc pass in -fast -sop mode
 2021-02-17 16:30:12 +01:00
Robert Baruch 1d79222af4 Fixes command line for abc pass in -fast -sop mode 2021-02-16 16:34:09 -08:00
Yosys Bot 78684596dc Bump version 2021-02-16 00:10:06 +00:00
Claire Xen 27d7741540
Merge pull request #2574 from dh73/master 
Accept disable case for SVA liveness properties.
 2021-02-15 17:49:11 +01:00
Yosys Bot 4e741adda9 Bump version 2021-02-13 00:10:04 +00:00
Zachary Snow 8de2e863af verilog: support recursive functions using ternary expressions 
This adds a mechanism for marking certain portions of elaboration as
occurring within unevaluated ternary branches. To enable elaboration of
the overall ternary, this also adds width detection for these
unelaborated function calls.
 2021-02-12 14:43:42 -05:00
gatecat 9f7cd10c98
Merge pull request #2585 from YosysHQ/dave/nexus-dotproduct 
nexus: Add MULTADDSUB9X9WIDE sim model
 2021-02-12 12:07:12 +00:00
Miodrag Milanovic 13c2fd7137 Ganulate Verific support 2021-02-12 10:08:43 +01:00
Yosys Bot 17c895cbf8 Bump version 2021-02-12 00:10:05 +00:00
whitequark 326f1c9db4
Merge pull request #2573 from zachjs/repeat-call 
verilog: refactored constant function evaluation
 2021-02-11 19:56:41 +00:00
Zachary Snow 73d611990d
Merge pull request #2578 from zachjs/genblk-port 
verlog: allow shadowing module ports within generate blocks
 2021-02-11 10:26:49 -05:00
Zachary Snow c383d156e9
Merge pull request #2584 from antmicro/atom_type_signedness 
verilog_parser: fix missing is_signed attribute in type_atom
 2021-02-11 10:26:06 -05:00
Kamil Rakoczy 7533534429 Add missing is_signed to type_atom 
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
 2021-02-11 15:05:38 +01:00
Zachary Snow 1d5f3fe506 verlog: allow shadowing module ports within generate blocks 
This is a somewhat obscure edge case I encountered while working on test
cases for earlier changes. Declarations in generate blocks should not be
checked against the list of ports. This change also adds a check
forbidding declarations within generate blocks being tagged as inputs or
outputs.
 2021-02-07 11:48:39 -05:00
Yosys Bot eff18a2b15 Bump version 2021-02-07 00:10:04 +00:00
whitequark 331de7a518
Merge pull request #2576 from zachjs/port-bind-sign-uniop 
genrtlil: fix signed port connection codegen failures
 2021-02-06 19:25:32 +00:00
Zachary Snow 4b2f977331 genrtlil: fix signed port connection codegen failures 
This fixes binding signed memory reads, signed unary expressions, and
signed complex SigSpecs to ports. This also sets `is_signed` for wires
generated from signed params when -pwires is used. Though not necessary
for any of the current usages, `is_signed` is now appropriately set when
the `extendWidth` helper is used.
 2021-02-05 19:51:30 -05:00
Yosys Bot 2f64f96129 Bump version 2021-02-06 00:10:05 +00:00
whitequark 3d9898272a
Merge pull request #2572 from antmicro/check-labels 
verilog_parser: add label check to gen_block
 2021-02-05 06:49:34 +00:00
Yosys Bot 7c6bf42db8 Bump version 2021-02-05 00:10:05 +00:00
Diego H c96eb2fbd7 Accept disable case for SVA liveness properties. 2021-02-04 15:35:35 -06:00