mirror of https://github.com/YosysHQ/yosys.git
machxo2: Use attrmvcp pass to move LOC and src attributes from ports/wires to IO cells.
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@ -188,3 +188,15 @@ module OSCH #(
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output SEDSTDBY
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);
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endmodule
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// IO- "$__" cells for the iopadmap pass. These are temporary cells not meant
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// to be instantiated by the end user. They are required in this file for
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// attrmvcp to work.
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(* blackbox *)
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module \$__FACADE_OUTPAD (input I, output O); endmodule
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(* blackbox *)
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module \$__FACADE_INPAD (input I, output O); endmodule
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(* blackbox *)
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module \$__FACADE_TOUTPAD (input I, OE, output O); endmodule
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(* blackbox *)
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module \$__FACADE_TINOUTPAD (input I, OE, output O, inout B); endmodule
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@ -154,7 +154,7 @@ struct SynthMachXO2Pass : public ScriptPass
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{
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if (check_label("begin"))
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{
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run("read_verilog -lib +/machxo2/cells_sim.v");
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run("read_verilog -lib -icells +/machxo2/cells_sim.v");
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run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
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}
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@ -184,7 +184,11 @@ struct SynthMachXO2Pass : public ScriptPass
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if (check_label("map_ios"))
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{
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if (!noiopad || help_mode)
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{
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run("iopadmap -bits -outpad $__FACADE_OUTPAD I:O -inpad $__FACADE_INPAD O:I -toutpad $__FACADE_TOUTPAD OE:I:O -tinoutpad $__FACADE_TINOUTPAD OE:O:I:B A:top", "(skip if '-noiopad')");
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run("attrmvcp -attr src -attr LOC t:$__FACADE_OUTPAD %x:+[O] t:$__FACADE_TOUTPAD %x:+[O] t:$__FACADE_TINOUTPAD %x:+[B]", "(skip if '-noiopad')");
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run("attrmvcp -attr src -attr LOC -driven t:$__FACADE_INPAD %x:+[I]", "(skip if '-noiopad')");
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}
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}
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if (check_label("map_ffs"))
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