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Merge pull request #2572 from antmicro/check-labels 

verilog_parser: add label check to gen_block
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whitequark 2021-02-05 06:49:34 +00:00 committed by GitHub
parent 7c6bf42db8 98c4feb72f
commit 3d9898272a
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2 changed files with 28 additions and 0 deletions
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2
frontends/verilog/verilog_parser.y
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@ -2794,6 +2794,8 @@ gen_block:
ast_stack.push_back(node);
} module_gen_body TOK_END opt_label {
exitTypeScope();
if ($3 != NULL && $7 != NULL && *$3 != *$7)
frontend_verilog_yyerror("Begin label (%s) and end label (%s) don't match.", $3->c_str()+1, $7->c_str()+1);
delete $3;
delete $7;
SET_AST_NODE_LOC(ast_stack.back(), @1, @7);

26
tests/verilog/block_labels.ys Normal file
View File

@ -0,0 +1,26 @@
read_verilog <<EOT
module foo;
genvar a = 0;
for (a = 0; a < 10; a++) begin : a
end : a
endmodule
EOT
read_verilog <<EOT
module foo2;
genvar a = 0;
for (a = 0; a < 10; a++) begin : a
end
endmodule
EOT
logger -expect error "Begin label \(a\) and end label \(b\) don't match\." 1
read_verilog <<EOT
module foo3;
genvar a = 0;
for (a = 0; a < 10; a++) begin : a
end : b
endmodule
EOT