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83 Commits

Author SHA1 Message Date
whitequark 7ff5a9db2d equiv_opt: pass -D EQUIV when techmapping. 
This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
 2018-12-07 17:20:34 +00:00
Olof Kindgren 889297c62a Only use non-blocking assignments of SB_RAM40_4K for yosys 
In an initial statement, blocking assignments are normally used
and e.g. verilator throws a warning if non-blocking ones are used.

Yosys cannot however properly resolve the interdependencies if
blocking assignments are used in the initialization of SB_RAM_40_4K
and thus this has been used.

This patch will change to use non-blocking assignments only for yosys
 2018-12-06 21:45:59 +01:00
Clifford Wolf 51f1bbeeb0 Add iCE40 SB_SPRAM256KA simulation model 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2018-09-10 11:57:24 +02:00
David Shah cd65eeb3b3 ice40: Add CIN_CONST and CIN_SET parameters to ICESTORM_LC 
Signed-off-by: David Shah <davey1576@gmail.com>
 2018-07-13 13:09:18 +02:00
Olof Kindgren faac2c5595 Avoid mixing module port declaration styles in ice40 cells_sim.v 
The current code requires workarounds for several simulators
For modelsim, the file must be compiled with -mixedansiports and
xsim needs --relax.
 2018-05-17 13:54:43 +02:00
Larry Doolittle efaef82f75 Squelch trailing whitespace, including meta-whitespace 2018-03-11 16:03:41 +01:00
Graham Edgecombe f93e6637aa Fix port names in SB_IO_OD 2017-12-10 15:33:38 +00:00
Graham Edgecombe 52ace35a73 Remove trailing comma from SB_IO_OD port list 
This isn't compatible with Icarus Verilog.
 2017-12-10 15:33:38 +00:00
David Shah 5e8d1922a4 Add remaining UltraPlus cells to ice40 techlib 2017-11-28 11:07:49 +00:00
David Shah 0505f1043c Remove unnecessary keep attributes 2017-11-18 17:53:21 +00:00
David Shah f9f3ca5da0 Add some UltraPlus cells to ice40 techlib 2017-11-16 12:24:35 +00:00
Clifford Wolf 0ccfb88728 Work around DDR dout sim glitches in ice40 SB_IO sim model 2016-02-07 11:19:48 +01:00
Clifford Wolf 4d0a6dac7b Merge pull request #108 from cseed/master 
Added LO to ICESTORM_LC for LUT cascade route.
 2015-12-07 03:32:20 +01:00
Cotton Seed 9f5b6e4cbc Added LO to ICESTORM_LC for LUT cascade route. 2015-12-06 17:24:48 -05:00
Clifford Wolf 3ad742056b Fixed iCE40 SB_IO OUTPUT_ENABLE vs. outena_q handling 2015-11-06 17:02:16 +01:00
Clifford Wolf 99ccb3180d Fixed ice40 handling of negclk RAM40 2015-09-10 17:35:19 +02:00
Clifford Wolf c43f38c81b Improved handling of "keep" attributes in hierarchical designs in opt_clean 2015-08-12 14:10:14 +02:00
Marcus Comstedt c9e56bc428 Added iCE40 WARMBOOT cell 2015-08-06 22:58:17 +02:00
Clifford Wolf 516e8828f2 Don't write a 17th memory bit in ice40/cells_sim (by Larry Doolittle) 2015-07-27 22:44:01 +02:00
Clifford Wolf c6ca4780e2 iCE40 DFF sim models: init Q regs to 0 2015-07-20 13:05:18 +02:00
Clifford Wolf 54588a276a Avoid tristate warning for blackbox ice40/cells_sim.v 2015-07-18 11:59:04 +02:00
Clifford Wolf 6c84341f22 Fixed trailing whitespaces 2015-07-02 11:14:30 +02:00
Clifford Wolf 09ef279b60 Added iCE40 PLL cells 2015-05-31 13:10:43 +02:00
Clifford Wolf 313f570fcc improved ice40 SB_IO sim model 2015-05-23 10:17:03 +02:00
Clifford Wolf 264eb8eb6e Added ice40 SB_IO sim model 2015-05-23 09:30:24 +02:00
Clifford Wolf 4cc4400514 improved iCE40 SB_RAM40_4K simulation model 2015-04-25 20:01:37 +02:00
Clifford Wolf 82a4722f46 More iCE40 bram improvements 2015-04-25 18:04:57 +02:00
Clifford Wolf 308a59aa18 iCE40 bram tests and fixes 2015-04-24 08:32:07 +02:00
Clifford Wolf 1277d1bcb8 iCE40: Added SB_RAM40_4K{,NR,NW,NRNW}* models 2015-04-19 21:37:40 +02:00
Clifford Wolf 31755ed1cf Changed ice40 ICESTORM_CARRYCONST port name 2015-04-16 12:09:14 +02:00
Clifford Wolf 0d344a23d3 improved ice40 dff cell mapping 2015-04-16 11:30:56 +02:00
Clifford Wolf 06ce496f8d more cells in ice40 cell library 2015-04-14 13:44:43 +02:00
Clifford Wolf 42d5d94a5d Added very first version of "synth_ice40" 2015-03-05 20:37:55 +01:00