2d573a0ff6
Merge pull request #1926 from YosysHQ/eddie/abc9_auto_dff
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abc9: support seq synthesis when module has (* abc9_flop *) and bypass non-combinatorial (* abc9_box *)
2020-05-18 08:06:50 -07:00
fa8cb3e35d
Revert "Add support for non-power-of-two mem chunks in verific importer"
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This reverts commit 173aa27ca5
2020-05-17 11:31:11 +02:00
39fa1e160d
verific: rewrite initial assume/asserts prior to elaboration
2020-05-15 14:05:28 -07:00
7101ef550b
verilog: attributes before task enable (but 13 s/r conflicts)
2020-05-14 16:10:11 -07:00
4017cc6380
aiger: -xaiger to return $_FF_ flops
2020-05-14 10:33:56 -07:00
6f4f795953
aiger/xaiger: use odd for negedge clk, even for posedge
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Since abc9 doesn't like negative mergeability values
2020-05-14 10:33:56 -07:00
483a190c1b
aiger: -xaiger to parse initial state back into (* init *) on Q wire
2020-05-14 10:33:56 -07:00
53fc3ed645
aiger: -xaiger to read $_DFF_[NP]_ back with new clocks created
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according to mergeability class, and init state as cell attr
2020-05-14 10:33:56 -07:00
5bcde7ccc3
Merge pull request #2045 from YosysHQ/eddie/fix2042
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verilog: error if no direction given for task arguments, default to input in SV mode
2020-05-14 09:45:54 -07:00
f02e20907e
Merge pull request #2052 from YosysHQ/claire/verific_memfix
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Add support for non-power-of-two mem chunks in verific importer
2020-05-14 18:45:13 +02:00
ee0beb481d
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
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ast: swap range regardless of range_left >= 0
2020-05-14 18:06:18 +02:00
173aa27ca5
Add support for non-power-of-two mem chunks in verific importer
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-14 14:38:13 +02:00
237962debd
verilog: default to input in sv mode if task/func has no dir ...
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otherwise error
2020-05-13 13:33:37 -07:00
17f050d3c6
Allow structs within structs.
2020-05-12 17:20:34 +01:00
f482c9c016
Generalise structs and add support for packed unions.
2020-05-12 14:25:33 +01:00
1f3003be7d
verilog: error out when non-ANSI task/func arguments
2020-05-11 13:00:36 -07:00
0b6b47ca67
Implement SV structs.
2020-05-08 14:40:49 +01:00
ebfdf61eb9
Merge pull request #2022 from Xiretza/fallthroughs
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Avoid switch fall-through warnings
2020-05-08 05:30:32 +00:00
0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990
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Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
2020-05-07 18:11:48 +02:00
695150b037
Add YS_FALLTHROUGH macro to mark case fall-through
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C++17 introduced [[fallthrough]], GCC and clang had their own vendored
attributes before that. MSVC doesn't seem to have such a warning at all.
2020-05-07 13:39:34 +02:00
a299e606f8
Merge pull request #2028 from zachjs/master
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verilog: allow null gen-if then block
2020-05-06 12:10:28 -07:00
8f9bba1bbf
verilog: allow null gen-if then block
2020-05-06 08:43:02 -04:00
323aa1df75
verilog: Move lexer location variables from global namespace to `VERILOG_FRONTEND` namespace.
2020-05-06 07:22:17 +00:00
283b1130a6
Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup
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frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-05 07:59:40 -07:00
7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src
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verilog: set src attribute for primitives
2020-05-05 06:49:18 -07:00
66d0ed2bcc
ast/simplify: don't bitblast async ROMs declared as `logic`.
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Fixes #2020 .
2020-05-05 04:16:59 +00:00
e936ac61ea
ast: swap range regardless of range_left >= 0
2020-05-04 12:18:20 -07:00
eb5eb60fd4
verilog: fix specify src attribute
2020-05-04 10:53:06 -07:00
22bf22fab4
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-04 10:48:37 -07:00
eca9fc01a7
verilog: set src attribute for primitives
2020-05-04 10:22:05 -07:00
584780d776
Merge pull request #1996 from boqwxp/rtlil_source_locations
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frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-04 08:58:50 -07:00
a0afa1787e
aiger: fixes for ports that have start_offset != 0
2020-05-02 10:00:32 -07:00
88185f8959
Fix handling of signed indices in bit slices
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
589ed2d970
Add AST_SELFSZ and improve handling of bit slices
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
bbbce0d1c5
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
bbde241942
Merge pull request #2001 from whitequark/wasi
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Add WASI platform support
2020-05-01 21:28:20 +00:00
d047ca8b11
Merge pull request #1981 from YosysHQ/claire/fix1837
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Clear current_scope when done with RTLIL generation
2020-05-01 14:58:41 +02:00
b0268b1311
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-01 07:17:27 +00:00
b43c282e4e
Add WASI platform support.
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This includes the following significant changes:
* Patching ezsat and minisat to disable resource limiting code
on WASM/WASI, since the POSIX functions they use are unavailable.
* Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
does not support spawning subprocesses (i.e. Emscripten or WASI).
This definition hides the definition of `run_command()`.
* Adding a new Makefile flag, DISABLE_SPAWN, present in the same
condition. This flag disables all passes that require spawning
subprocesses for their function.
2020-04-30 18:56:25 +00:00
5017ff4a97
verific: ignore anonymous enums
2020-04-30 07:48:47 -07:00
97bfe65d3a
verific: support VHDL enums too
2020-04-27 15:17:13 -07:00
adb483ddfd
frontends/json/jsonparse.cc: Like the upto field read_json can also read the signedness of a wire
2020-04-27 10:36:18 -07:00
5f9cd2e2f6
Preserve 'signed'-ness of a verilog wire through RTLIL
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As per suggestion made in https://github.com/YosysHQ/yosys/pull/1987 , now:
RTLIL::wire holds an is_signed field.
This is exported in JSON backend
This is exported via dump_rtlil command
This is read in via ilang_parser
2020-04-27 09:44:24 -07:00
dd5f206d9e
verific: recover wiretype/enum attr as part of import_attributes()
2020-04-27 08:43:54 -07:00
b52eccef3a
Revert "verific: import enum attributes from verific"
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This reverts commit 5028e17f7d
2020-04-24 11:57:55 -07:00
d3555c667c
verific: do not assert if wire not found; warn instead
2020-04-23 16:28:11 -07:00
5028e17f7d
verific: import enum attributes from verific
2020-04-22 17:26:56 -07:00
9f1fb11b1d
Clear current_scope when done with RTLIL generation, fixes #1837
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-22 14:51:20 +02:00
06a344efcb
ilang, ast: Store parameter order and default value information.
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Fixes #1819 , #1820 .
2020-04-21 19:09:00 +02:00
9e1afde7a0
Merge pull request #1851 from YosysHQ/claire/bitselwrite
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Improved rewrite code for writing to bit slice
2020-04-21 18:46:52 +02:00
abc8f1fcb6
Merge pull request #1961 from whitequark/paramod-original-name
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ast, rpc: record original name of $paramod\* as \hdlname attribute
2020-04-21 01:43:20 +00:00
35990b95ec
Extend support for format strings in Verilog front-end
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-18 14:08:51 +02:00
41421f5dca
ast, rpc: record original name of $paramod\* as \hdlname attribute.
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The $paramod name mangling is not invertible (the \ character, which
separates the module name from the parameters, is valid in the module
name itself), which does not stop people from trying to invert it.
This commit makes it easy to invert the name mangling by storing
the original name explicitly, and fixes the firrtl backend to use
the newly introduced attribute.
2020-04-18 03:47:28 +00:00
00d74f0b9c
Set Verilog source location for explicit blocks (`begin` ... `end`).
2020-04-17 06:23:03 +00:00
10a814f978
Add Verilog source location information to `AST_POSEDGE` and `AST_NEGEDGE` nodes.
2020-04-17 06:16:59 +00:00
9253497358
Add location information to `AST_CONSTANT` nodes.
2020-04-16 19:11:47 +00:00
e86ba3b94d
Make mask-and-shift the default for bitselwrite
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-16 12:11:52 +02:00
e1fb12a4b9
Add LookaheadRewriter for proper bitselwrite support
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-16 12:11:07 +02:00
4d02505820
ast: Fix handling of identifiers in the global scope
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-16 10:30:07 +01:00
4711fea6c0
Improved rewrite code for writing to bit slice (disabled for now)
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This adds the new rewrite rule. But it's still missing a check that makes
sure the new rewrite rule is actually a valid substitute in the always
block being processed. Therefore the new rewrite rule is just disabled
for now.
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-15 17:44:37 +02:00
2d436bc4f1
Merge pull request #1918 from whitequark/simplify-improve_enum
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ast/simplify: improve enum handling
2020-04-15 14:16:50 +00:00
2106f78bb1
ast/simplify: improve enum handling.
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Before this commit, enum values were serialized as attributes of form
\enum_<width>_<value>
where <value> was a decimal signed integer.
This has multiple drawbacks:
* Enums with large values would be hard to process for downstream
tooling that cannot parse arbitrary precision decimals. (In fact
Yosys also did not correctly process enums with large values,
and would overflow `int`.)
* Enum value attributes were not confined to their own namespace,
making it harder for downstream tooling to enumerate all such
attributes, as opposed to looking up any specific value.
* Enum values could not include x or z, which are explicitly
permitted in the SystemVerilog standard.
After this commit, enum values are serialized as attributes of form
\enum_value_<value>
where <value> is a bit sequence of the appropriate width.
2020-04-15 14:14:50 +00:00
9b4dab397e
Fix 5bba9c3, closes #1876
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-04-14 21:05:07 +02:00
f41c7ccfff
Merge pull request #1879 from jjj11x/jjj11x/package_decl
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support using previously declared types/localparams/parameters in package
2020-04-14 12:40:00 +00:00
0e1beb6f30
Merge pull request #1880 from jjj11x/duplicate_enum
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duplicated enum item names should result in an error
2020-04-14 12:39:28 +00:00
5448f9c85d
Merge pull request #1910 from boqwxp/cleanup_ilang_parser
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Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
2020-04-13 08:40:45 +00:00
8a84674a42
Clean up pseudo-private member usage in `frontends/ilang/ilang_parser.y`.
2020-04-13 04:22:00 +00:00
0a178de1b3
verilog: Fix write to deleted object
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-12 18:49:09 +01:00
f1d9ca1563
Merge pull request #1875 from whitequark/read_ilang-int_overflow
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Improve handling of integer literals in RTLIL frontend
2020-04-09 04:02:57 +00:00
c15040c218
aigerparse: only define __STDC_FORMAT_MACROS it not already before.
2020-04-07 12:50:31 -07:00
dbfd6b7530
duplicated enum item names should result in an error
2020-04-07 02:30:11 -04:00
249876b614
support using previously declared types/localparams/params in package
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(parameters in systemverilog packages can't actually be overridden, so
allowing parameters in addition to localparams doesn't actually add any
new functionality, but it's useful to be able to use the parameter
keyword also)
2020-04-07 00:38:15 -04:00
b494d4c656
read_ilang: improve style. NFC.
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Co-Authored-By: Alberto Gonzalez <61295559+boqwxp@users.noreply.github.com>
2020-04-06 18:31:15 +00:00
d22888ce74
read_ilang: improve error message for overly long wires.
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Fixes #1838 .
2020-04-06 10:33:02 +00:00
ca70a1049f
read_ilang: detect overflow of integer literals.
2020-04-06 10:32:02 +00:00
cf716e1fff
Merge pull request #1853 from YosysHQ/eddie/fix_dynslice
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ast: cap dynamic range select to size of signal, suppresses warnings
2020-04-02 12:27:10 -07:00
5f662b1c43
Merge pull request #1767 from YosysHQ/eddie/idstrings
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IdString: use more ID::*, make them easier to use, speed up IdString::in()
2020-04-02 11:47:25 -07:00
956ecd48f7
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
c69f4b246a
Merge pull request #1846 from dh73/ast_fe
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Adding error message for when size (width) of number literal is zero
2020-04-02 18:15:15 +02:00
fdafb74eb7
kernel: use more ID::*
2020-04-02 07:14:08 -07:00
37f42fe102
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup
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kernel: speedup by using more pass-by-const-ref
2020-04-02 07:13:33 -07:00
f3405e7c79
Merge pull request #1844 from YosysHQ/dave/gen-source-loc
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verilog: Add location info for generate constructs
2020-04-01 20:55:24 +01:00
c3997c77a5
verilog: Add location info for generate constructs
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Signed-off-by: David Shah <dave@ds0.me>
2020-04-01 18:47:20 +01:00
c22fb76664
ast: cap dynamic range select to size of signal, suppresses warnings
2020-04-01 09:59:23 -07:00
926a010b49
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice
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ast: simplify to fully populate dynamic slicing case transformation
2020-04-01 08:38:14 +02:00
5132f4099b
ast: simplify to fully populate dynamic slicing case transformation
2020-03-31 11:52:14 -07:00
c859bcf71b
Replacing log_error for log_file_error due consistency
2020-03-31 12:01:29 -06:00
92809bb1d3
Adding error message for when size (width) of number literal is zero
2020-03-30 17:18:13 -06:00
05f74d4f31
Merge pull request #1783 from boqwxp/astcc_cleanup
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Clean up pseudo-private member usage in `frontends/ast/ast.cc`.
2020-03-30 13:06:10 -07:00
b538c6fbf2
Add explanatory comment about inefficient wire removal and remove superfluous call to `fixup_ports()`.
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Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-03-30 18:14:32 +00:00
d5e2061687
Merge pull request #1811 from PeterCrozier/typedef_scope
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Support module/package/interface/block scope for typedef names.
2020-03-30 13:55:39 +02:00
2c847e7efe
Merge pull request #1778 from rswarbrick/sv-defines
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Add support for SystemVerilog-style `define to Verilog frontend
2020-03-30 13:51:12 +02:00
1bf2bdf05b
Merge pull request #1607 from whitequark/simplify-simplify-meminit
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ast: avoid intermediate wires/assigns when lowering to AST_MEMINIT
2020-03-27 17:28:26 +01:00
f8c065ed1c
Inline productions to follow house style.
2020-03-27 16:21:45 +00:00
044ca9dde4
Add support for SystemVerilog-style `define to Verilog frontend
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This patch should support things like
`define foo(a, b = 3, c) a+b+c
`foo(1, ,2)
which will evaluate to 1+3+2. It also spots mistakes like
`foo(1)
(the 3rd argument doesn't have a default value, so a call site is
required to set it).
Most of the patch is a simple parser for the format in preproc.cc, but
I've also taken the opportunity to wrap up the "name -> definition"
map in a type, rather than use multiple std::map's.
Since this type needs to be visible to code that touches defines, I've
pulled it (and the frontend_verilog_preproc declaration) out into a
new file at frontends/verilog/preproc.h and included that where
necessary.
Finally, the patch adds a few tests in tests/various to check that we
are parsing everything correctly.
2020-03-27 16:08:26 +00:00
6040593994
Revert over-aggressive change to a more modest cleanup.
2020-03-27 09:46:40 +00:00
9a8a644ad1
Error duplicate declarations of a typedef name in the same scope.
2020-03-24 14:35:21 +00:00
ecc22f7fed
Support module/package/interface/block scope for typedef names.
2020-03-23 20:07:22 +00:00
6cad865d12
Simplify was not being called for packages. Broke typedef enums.
2020-03-22 18:20:46 -07:00
c06eda2504
Build pkg_user_types before parsing in case of changes in the design.
2020-03-22 18:20:46 -07:00
Eddie Hung
Claire Wolf
Claire Wolf
Peter Crozier
whitequark
Xiretza
Zachary Snow
Alberto Gonzalez
Vamsi K Vytla
Marcelina Kościelnicka
David Shah
Henner Zeller
Jeff Wang
Diego H
N. Engelhardt
Rupert Swarbrick