Clifford Wolf
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a362fd81ae
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Fixed O(n^2) performance bug in verilog preprocessor
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2013-11-22 14:08:43 +01:00 |
Clifford Wolf
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e4429c480e
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Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)
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2013-11-22 12:46:02 +01:00 |
Clifford Wolf
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92035fb38e
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Implemented indexed part selects
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2013-11-20 13:05:27 +01:00 |
Clifford Wolf
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0f04738f40
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Added "synthesis" in (synopsys|synthesis) comment support
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2013-11-20 11:44:09 +01:00 |
Clifford Wolf
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19dba2561e
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Implemented part/bit select on memory read
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2013-11-20 10:51:32 +01:00 |
Clifford Wolf
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e340532ce5
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Added init= attribute for fpga-style reset values
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2013-11-20 01:49:37 +01:00 |
Clifford Wolf
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0dfdbd991a
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Fixed parsing of module arguments when one type is used for many args
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2013-11-19 20:35:31 +01:00 |
Clifford Wolf
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63060dcd2e
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Fixed parsing of "parameter integer"
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2013-11-13 15:30:23 +01:00 |
Clifford Wolf
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f050c40519
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Various fixes for correct parameter support
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2013-11-07 10:02:11 +01:00 |
Clifford Wolf
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23cf23418c
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Fixed handling of boolean attributes (frontends)
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2013-10-24 11:20:13 +02:00 |
Clifford Wolf
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eae43e2db4
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Fixed handling of boolean attributes (kernel)
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2013-10-24 10:59:27 +02:00 |
Johann Glaser
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f352205635
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fixed Verilog parser filename and line numbering issue with include files
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2013-08-21 09:20:59 +02:00 |
Johann Glaser
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a99c224157
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Added support for include directories with the new '-I' argument of the
'read_verilog' command
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2013-08-20 15:48:16 +02:00 |
Johann Glaser
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6c4cbc03c2
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Added support for notif0/notif1 primitives
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2013-08-20 11:23:59 +02:00 |
Clifford Wolf
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8656b1c08f
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Added support for bufif0/bufif1 primitives
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2013-08-19 19:50:04 +02:00 |
Clifford Wolf
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4214561890
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Improved ast dumping (ast/verilog frontend)
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2013-08-19 19:49:14 +02:00 |
Clifford Wolf
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00a6c1d9a5
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Major redesign of expr width/sign detecion (verilog/ast frontend)
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2013-07-09 14:31:57 +02:00 |
Clifford Wolf
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56432a920f
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Added defparam support to Verilog/AST frontend
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2013-07-04 14:12:33 +02:00 |
Clifford Wolf
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0c6ffc4c65
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More fixes for bugs found using xsthammer
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2013-06-13 11:18:45 +02:00 |
Clifford Wolf
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4b311b7b99
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Further improved and extended xsthammer
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2013-06-11 19:49:35 +02:00 |
Clifford Wolf
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db98a18edb
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Enabled AST/Verilog front-end optimizations per default
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2013-06-10 13:19:04 +02:00 |
Clifford Wolf
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46fbe9d262
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Added SAT generator and simple sat_solve command
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2013-06-07 13:59:13 +02:00 |
Johann Glaser
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10a195c0a1
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added option '-Dname[=definition]' to command 'read_verilog'
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2013-05-19 17:07:52 +02:00 |
Clifford Wolf
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b56e06d2f5
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Added support for verilog === operator
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2013-05-07 14:35:40 +02:00 |
Clifford Wolf
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161565be10
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Added AST_INITIAL (before verilog "initial" was mapped to AST_ALWAYS)
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2013-03-31 11:19:11 +02:00 |
Clifford Wolf
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7bfc7b61a8
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Implemented proper handling of stub placeholder modules
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2013-03-28 09:20:10 +01:00 |
Clifford Wolf
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7a99349de4
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Improvements and bugfixes for generate blocks with local signals
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2013-03-26 11:31:34 +01:00 |
Clifford Wolf
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df9753d398
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Added mem2reg option to verilog frontend
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2013-03-24 11:13:32 +01:00 |
Clifford Wolf
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e45d1c8865
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Tiny fixes to verilog parser
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2013-03-23 18:54:31 +01:00 |
Clifford Wolf
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8a6b0a3520
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Added help messages to ilang and verilog frontends
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2013-03-01 08:03:00 +01:00 |
Clifford Wolf
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a321a5c412
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Moved stand-alone libs to libs/ directory and added libs/subcircuit
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2013-02-27 09:32:19 +01:00 |
Clifford Wolf
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4f0c2862a0
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Added support for verilog genblock[index].member syntax
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2013-02-26 13:18:22 +01:00 |
Clifford Wolf
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6d1502b948
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Added support for "always @(*)"
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2013-01-16 17:32:11 +01:00 |
Clifford Wolf
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6543917fb8
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added .gitignore files
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2013-01-05 11:19:11 +01:00 |
Clifford Wolf
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7764d0ba1d
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initial import
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2013-01-05 11:13:26 +01:00 |