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3765 Commits

Author SHA1 Message Date
Clifford Wolf 104b9dc96b Disable OSX in .travis.yml 2017-10-25 15:17:29 +02:00
Clifford Wolf 9a038861c8 Add ENABLE_DEBUG config flag 2017-10-25 14:57:16 +02:00
Clifford Wolf af36755e0a Update ABC to hg rev f6838749f234 2017-10-25 14:51:59 +02:00
Clifford Wolf a8cf431d9c Remove vhdl2verilog 2017-10-25 14:50:22 +02:00
Clifford Wolf c672c321e3 Capsulate smt-solver read/write in separate functions 2017-10-25 13:37:11 +02:00
Clifford Wolf dd46d76394 Fix a bug in yosys-smtbmc in ROM handling 2017-10-25 13:05:14 +02:00
Clifford Wolf baddb017fe Remove PSL example from tests/sva/ 2017-10-20 13:16:24 +02:00
Clifford Wolf 0a31a0b3ae Remove all PSL support code from verific.cc 2017-10-20 13:14:04 +02:00
Clifford Wolf 309f8fe74f Merge pull request #437 from mithro/master 
Adding COPYING file with license information.
 2017-10-20 11:44:54 +02:00
Tim 'mithro' Ansell 19aa261527 Adding COPYING file with license information. 
This allows GitHub and other tools to detect the license info. Providing
a COPYING for LICENSE file is also pretty standard.
 2017-10-19 20:22:12 -04:00
Clifford Wolf 716dbc9274 Revert 90be0d8 as it causes endless loops for some designs 2017-10-14 11:57:25 +02:00
Clifford Wolf 1954c78ea7 Add "verific -vlog-libdir" 2017-10-13 20:23:19 +02:00
Clifford Wolf e7a3c47cc7 Add "verific -vlog-incdir" and "verific -vlog-define" 2017-10-13 20:12:51 +02:00
Clifford Wolf 05068af880 Update Verific README 2017-10-13 17:11:53 +02:00
Clifford Wolf d565bc4a82 Merge pull request #434 from Kmanfi/vector_fix 
Fix input vector for reduce cells.
 2017-10-12 12:16:47 +02:00
Kaj Tuomi 90be0d800b Fix input vector for reduce cells. 2017-10-12 13:05:10 +03:00
Clifford Wolf bc5cc4e103 Add Verific fairness/liveness support 2017-10-12 12:00:09 +02:00
Clifford Wolf 2b03a73a46 Update ABC to hg rev 6283c5d99b06 2017-10-11 13:58:51 +02:00
Clifford Wolf 12c10892e6 Merge branch 'master' of github.com:cliffordwolf/yosys 2017-10-10 15:16:45 +02:00
Clifford Wolf c10e96c9ec Start work on pre-processor for Verific SVA properties 2017-10-10 15:16:39 +02:00
Clifford Wolf 7c57d8fbb4 Rewrite ABC output to include proper net names in timing report 2017-10-10 13:32:58 +02:00
Clifford Wolf 142f4ca03a Add timing constraints to osu035 example 2017-10-10 13:32:04 +02:00
Clifford Wolf bc80426d45 Remove some dead code 2017-10-10 12:00:48 +02:00
Clifford Wolf caa78388cd Allow $past, $stable, $rose, $fell in $global_clock blocks 2017-10-10 11:59:32 +02:00
Clifford Wolf adf1754729 Add $shiftx support to verilog front-end 2017-10-07 13:40:54 +02:00
Clifford Wolf 2b04e8caa6 Update ABC to hg rev 0fc1803a77c0 2017-10-06 10:07:33 +02:00
Larry Doolittle 50bcd9a728 Clean whitespace and permissions in techlibs/intel 2017-10-05 16:23:49 +02:00
Clifford Wolf fc3378916d Improve handling of Verific errors 2017-10-05 14:38:32 +02:00
Clifford Wolf ee56a887b6 Improve Verific error handling, check VHDL static asserts 2017-10-04 18:56:28 +02:00
Clifford Wolf 3f22f48eeb Add blackbox command 2017-10-04 18:30:42 +02:00
Clifford Wolf b92ff2706e Fix nasty bug in Verific bindings 2017-10-04 17:23:42 +02:00
Clifford Wolf a381188b92 Merge branch 'pr_ast_const_funcs' of https://github.com/udif/yosys 2017-10-03 18:23:45 +02:00
Clifford Wolf 983479f395 Merge branch 'fix_shift_reduce_conflict' of https://github.com/udif/yosys 2017-10-03 18:20:08 +02:00
Clifford Wolf b4fd7ecd83 Merge branch 'dh73-master' 2017-10-03 17:33:43 +02:00
Clifford Wolf 65f91e5120 Rename "write_verilog -nobasenradix" to "write_verilog -decimal" 2017-10-03 17:31:21 +02:00
dh73 4718e65763 Tested and working altsyncarm without init files 2017-10-01 19:59:45 -05:00
dh73 e480847753 Fixed wrong declaration in Verilog backend 2017-10-01 11:11:32 -05:00
dh73 cbaba62401 Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now 2017-10-01 11:04:17 -05:00
Udi Finkelstein eb40278a16 Turned a few member functions into const, esp. dumpAst(), dumpVlog(). 2017-09-30 07:37:38 +03:00
Udi Finkelstein 72a08eca3d Resolved classical Bison IF/THEN/ELSE shift/reduce conflict using the textbook solution 
(Oreilly 'Flex & Bison' page 189)
 2017-09-30 06:39:07 +03:00
Clifford Wolf c5b204d8d2 Add first draft of eASIC back-end 2017-09-29 17:53:43 +02:00
Clifford Wolf e64b9d5a4d Fix synth_ice40 doc regarding -top default 2017-09-29 17:52:57 +02:00
Clifford Wolf dbfd8460a9 Allow $size and $bits in verilog mode, actually check test case 2017-09-29 11:56:43 +02:00
Clifford Wolf 637a02eb5c Merge pull request #425 from udif/udif_dollar_bits 
Add $bits() and $size()
 2017-09-29 11:39:36 +02:00
Clifford Wolf 29f8acf095 Merge pull request #421 from stephengroat/osx-travis 
Add osx tests using brew bundle
 2017-09-28 14:45:47 +02:00
Stephen 57b3c34e69 delete bad backslash 2017-09-27 16:52:20 -07:00
Stephen 1ba06cefcc forgot to install bundles 2017-09-27 16:51:50 -07:00
Stephen Groat de0797f073 Add osx tests using brew bundle 2017-09-27 16:49:03 -07:00
Clifford Wolf 30396270a2 Increase maximum LUT size in blifparse to 12 bits 2017-09-27 15:27:42 +02:00
Udi Finkelstein e951ac0dfb $size() now works correctly for all cases! 
It seems the issues was that AST_MULTIRANGE is converted into a multirange_dimensions[] array on the AST_MEMORY node directly.
 2017-09-26 20:34:24 +03:00