riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
8,271 Commits 90 Branches 49 Tags 38 MiB
Commit Graph

8271 Commits

Author SHA1 Message Date
SergeyDegtyar 489444bcba Fix latches.ys test 2019-10-17 17:10:02 +02:00
SergeyDegtyar 6331fa5b02 Remove xilinx_ug901 tests (will be moved to yosys-tests) 2019-10-17 17:10:02 +02:00
SergeyDegtyar 757c476f62 Add smoke tests to tests/xilinx 2019-10-17 17:10:02 +02:00
SergeyDegtyar ca7a58bcc8 Add comments for unproven cells. 2019-10-17 17:08:38 +02:00
SergeyDegtyar 2ae7dec530 Add tests for Xilinx UG901 examples 2019-10-17 17:08:38 +02:00
Clifford Wolf 0d037bf9d8
Merge pull request #1450 from YosysHQ/clifford/fixdffmux 
Fix handling of init attributes in peepopt dffmux pattern
 2019-10-16 14:44:38 +02:00
Clifford Wolf b8774ae849 Fix dffmux peepopt init handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-16 11:40:32 +02:00
Clifford Wolf bb0851bfc5 Move GENERATE_PATTERN macro to separate utility header 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-16 11:40:01 +02:00
Pepijn de Vos 72323e11a4 remove duplicate DFFR 2019-10-16 11:24:56 +02:00
Clifford Wolf af61d92441 Disable left-over log_debug in peepopt_dffmux.pmg 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-16 10:43:47 +02:00
Clifford Wolf 71936209cf Fix parsing of .cname BLIF statements 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-16 09:06:57 +02:00
Clifford Wolf 935d3e19e2 Add .blackbox support to blif front-end 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-16 00:00:27 +02:00
Benedikt Tutzer f8f572fbfc Merge branch 'master' of https://github.com/YosysHQ/yosys into feature/python_wrappers/globals_and_streams 2019-10-15 10:13:21 +02:00
Clifford Wolf 2daa56859f
Merge pull request #1448 from YosysHQ/daveshah1-sv-experiments 
Typedef support (with wrong syntax)
 2019-10-14 16:49:15 +02:00
David Shah e909f29ca3
Merge pull request #1446 from YosysHQ/dave/ecp5-ioff 
ecp5: Use IOLOGIC flipflops
 2019-10-14 14:05:54 +01:00
Clifford Wolf e84cedfae4 Use "(id)" instead of "id" for types as temporary hack 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-10-14 05:24:31 +02:00
David Shah e1d4e683b4 ecp5: Add ECLKBRIDGECS blackbox 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-11 14:50:33 +01:00
David Shah 7b1a6706d8 ecp5: Add attrmvcp to copy syn_useioff to driving FF 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-10 15:58:31 +01:00
David Shah 3b44e80d4b ecp5: Set syn_useioff on IO FFs to enable packing 
Signed-off-by: David Shah <dave@ds0.me>
 2019-10-10 15:55:16 +01:00
Miodrag Milanović 3c6a566d86
Merge pull request #1445 from YosysHQ/mwk/xilinx_ibufg 
xilinx: Add simulation model for IBUFG.
 2019-10-10 14:09:32 +02:00
Marcin Kościelnicki 526fe4cb89 xilinx: Add simulation model for IBUFG. 2019-10-10 13:16:03 +02:00
Benedikt Tutzer 79be986e22 Fix renaming all classes to Cpp* 
(This is only relevant for classes that are exposed twice, one time as a
base class and one time as a derived class that can in turn be
overridden in python, but actually all others were renamed)
 2019-10-09 14:21:52 +02:00
Benedikt Tutzer 9c59a56aa4 Expose global variables and allow logging to python streams 
Global variables are now accessible via the Yosys class.
To capture Yosys output, once can now register an output stream in
Pyosys.
 2019-10-09 13:59:35 +02:00
Eddie Hung 304e5f9ea4 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-08 13:03:06 -07:00
Eddie Hung 3fb604c75d Revert "Add test that is expecting to fail" 
This reverts commit c28d4b8047.
 2019-10-08 12:41:26 -07:00
Eddie Hung ea54b5ea61 Revert "Be mindful that sigmap(wire) could have dupes when checking \init" 
This reverts commit f46ac1df9f.
 2019-10-08 12:41:24 -07:00
Eddie Hung cfc181cba9
Merge pull request #1432 from YosysHQ/eddie/fix1427 
Refactor peepopt_dffmux and be sensitive to \init when trimming
 2019-10-08 12:38:29 -07:00
Eddie Hung 4c89a4e642
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync 
async2sync to be called by equiv_opt only when -async2sync given
 2019-10-08 10:53:44 -07:00
Eddie Hung 9fd2ddb14c
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 
Rename abc_* names/attributes to more precisely be abc9_*
 2019-10-08 10:53:38 -07:00
Eddie Hung 472b5d33a6
Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_comments 
Add notes and comments for xilinx_dsp
 2019-10-08 10:53:30 -07:00
Eddie Hung 4f0818275f Cleanup 2019-10-07 15:58:55 -07:00
Eddie Hung b2e34f932a Rename $currQ to $abc9_currQ 2019-10-07 15:31:43 -07:00
Eddie Hung 2cb2116b4c Use "abc9_period" attribute for delay target 2019-10-07 15:03:44 -07:00
Eddie Hung 90a954bb9c Get rid of latch_* in write_xaiger 2019-10-07 13:09:13 -07:00
Eddie Hung bae3d8705d Update comments in abc9_map.v 2019-10-07 12:54:45 -07:00
Eddie Hung 1dc22607c3 Remove -D_ABC9 2019-10-07 12:21:52 -07:00
Eddie Hung 1504ca2cd9 Remove "write_xaiger -zinit" 2019-10-07 11:58:49 -07:00
Eddie Hung e1554b56dd Add comment on default flop init 2019-10-07 11:56:17 -07:00
Eddie Hung d9fba95177 Get rid of output_port lookup 2019-10-07 11:49:06 -07:00
Clifford Wolf 4072a96663
Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarry 
Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
 2019-10-06 12:11:20 +02:00
Eddie Hung 3879ca1398 Do not require changes to cells_sim.v; try and work out comb model 2019-10-05 22:55:18 -07:00
Eddie Hung 5c68da4150 Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf 2019-10-05 09:27:12 -07:00
Clifford Wolf 10d0bad67e
Update README.md 2019-10-05 18:13:04 +02:00
Eddie Hung 3c6e5d82a6 Error if $currQ not found 2019-10-05 09:06:13 -07:00
Eddie Hung f90a4b1e24 Missed this 2019-10-05 08:57:37 -07:00
Eddie Hung 991c2ca95b Add comment on why we have to match for clock-enable/reset muxes 2019-10-05 08:56:37 -07:00
Eddie Hung ebb059896a Add note on pattern detector 2019-10-05 08:53:01 -07:00
Miodrag Milanović 7c074ef844
Merge pull request #1436 from YosysHQ/mmicko/msvc_fix 
Fixes for MSVC build
 2019-10-05 07:48:30 +02:00
Eddie Hung 6c5e1234e1 Add comment on why partial multipliers are 18x18 2019-10-04 22:31:04 -07:00
Eddie Hung 792cd31052 Add comments for xilinx_dsp_cascade 2019-10-04 22:31:04 -07:00