Commit Graph

940 Commits

Author SHA1 Message Date
Eddie Hung ba9513b325 Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-28 09:30:53 -07:00
Eddie Hung f745727de5 read_aiger to only clean own design 2019-05-28 08:45:10 -07:00
Eddie Hung 3eec100748 Parse "a" extension and boxes from map file 2019-05-27 23:11:21 -07:00
Eddie Hung 428d7c8e11 Remove unused function 2019-05-27 13:49:42 -07:00
Eddie Hung e115e736fa parse_xaiger to not parse symbol table 2019-05-27 12:34:17 -07:00
Eddie Hung 234156c01a Instantiate cell type (from sym file) otherwise 'clean' warnings 2019-05-27 12:16:10 -07:00
Eddie Hung 03b289a851 Add 'cinput' and 'coutput' to symbols file for boxes 2019-05-27 11:38:52 -07:00
Stefan Biereigel 816082d5a1
Merge branch 'master' into wandwor 2019-05-27 19:07:46 +02:00
Stefan Biereigel cd12f2ddcf remove leftovers from ast data structures 2019-05-27 18:01:44 +02:00
Stefan Biereigel ed625a3102 move wand/wor resolution into hierarchy pass 2019-05-27 18:00:22 +02:00
Clifford Wolf 92dde319fc
Merge pull request #1044 from mmicko/invalid_width_range
Give error instead of asserting for invalid range, fixes #947
2019-05-27 13:26:12 +02:00
Miodrag Milanovic 84ffb21708 Give error instead of asserting for invalid range, fixes #947 2019-05-27 12:25:18 +02:00
Miodrag Milanovic 34417ce55f Added support for unsized constants, fixes #1022
Includes work from @sumit0190 and @AaronKel
2019-05-27 11:42:10 +02:00
Eddie Hung 68359bcd6f Merge remote-tracking branch 'origin/eddie/opt_rmdff' into xc7mux 2019-05-23 13:37:53 -07:00
Stefan Biereigel 85de9d26c1 fix assignment of non-wires 2019-05-23 17:55:56 +02:00
Stefan Biereigel fd003e0e97 fix indentation across files 2019-05-23 13:57:27 +02:00
Stefan Biereigel 075a48d3fa implementation for assignments working 2019-05-23 13:57:27 +02:00
Stefan Biereigel 9df04d7e75 make lexer/parser aware of wand/wor net types 2019-05-23 13:57:27 +02:00
Eddie Hung 7057753427 Rename label 2019-05-21 18:20:31 -07:00
Eddie Hung b5a29460b9 Try again 2019-05-21 17:20:19 -07:00
Eddie Hung 1bff09f2ff Fix warning 2019-05-21 16:26:20 -07:00
Eddie Hung fb09c6219b Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-21 14:21:00 -07:00
Kaj Tuomi 48ddbe52fb Read bigger Verilog files.
Hit parser limit with 3M gate design. This commit fix it.
2019-05-18 14:20:30 +03:00
Clifford Wolf b6345b111d
Merge pull request #1013 from antmicro/parameter_attributes
Support for attributes on parameters and localparams for Verilog frontend
2019-05-16 14:21:18 +02:00
Maciej Kurc ce4a0954bc Added support for parsing attributes on parameters in Verilog frontent. Content of those attributes is ignored.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
2019-05-16 12:44:16 +02:00
Henner Zeller 8eb2798776 Make the generated *.tab.hh include all the headers needed to define the union. 2019-05-14 21:07:26 -07:00
Clifford Wolf 752553d8e9
Merge pull request #946 from YosysHQ/clifford/specify
Add specify parser
2019-05-06 20:57:15 +02:00
Clifford Wolf 1706798f4e
Merge pull request #975 from YosysHQ/clifford/fix968
Re-enable "final loop assignment" feature and fix opt_clean warnings
2019-05-06 20:53:38 +02:00
Clifford Wolf 7bab7b3d49
Merge pull request #871 from YosysHQ/verific_import
Improve verific -chparam and add hierarchy -chparam
2019-05-06 20:51:59 +02:00
Clifford Wolf d187be39d6 Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968 2019-05-06 15:41:13 +02:00
Clifford Wolf 20268d12a5 Fix the other bison warning in ilang_parser.y
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 15:38:43 +02:00
Clifford Wolf 1cd1b5fc1a Add "real" keyword to ilang format
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-06 12:00:40 +02:00
Clifford Wolf c7f2e93024 Merge branch 'master' of github.com:YosysHQ/yosys into clifford/specify 2019-05-06 11:46:10 +02:00
Ben Widawsky a98069d762 verilog_parser: Fix Bison warning
As of Bison 2.6, name-prefix is deprecated. This fixes
frontends/verilog/verilog_parser.y:99.1-34: warning: deprecated directive, use ‘%define api.prefix {frontend_verilog_yy}’ [-Wdeprecated]
 %name-prefix "frontend_verilog_yy"

For details: https://www.gnu.org/software/bison/manual/html_node/Multiple-Parsers.html

Compile tested only.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2019-05-05 19:36:27 -07:00
Clifford Wolf 70d0f389ad
Merge pull request #988 from YosysHQ/clifford/fix987
Add approximate support for SV "var" keyword
2019-05-04 21:58:25 +02:00
Clifford Wolf 66d6ca2de2 Add support for SVA "final" keyword
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 09:25:32 +02:00
Clifford Wolf 87426f5a06 Improve write_verilog specify support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 08:46:24 +02:00
Clifford Wolf 9804c86e87 Add approximate support for SV "var" keyword, fixes #987
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-04 07:52:51 +02:00
Eddie Hung d9c4644e88 Merge remote-tracking branch 'origin/master' into clifford/specify 2019-05-03 15:05:57 -07:00
Eddie Hung c7d7d8ad1b For hier_tree::Elaborate() also include SV root modules (bind) 2019-05-03 20:53:25 +02:00
Eddie Hung 3ea54ec400 Fix verific_parameters construction, use attribute to mark top netlists 2019-05-03 20:53:25 +02:00
Eddie Hung a27b42e975 WIP -chparam support for hierarchy when verific 2019-05-03 20:53:25 +02:00
Eddie Hung 0f1a4cc03c verific_import() changes to avoid ElaborateAll() 2019-05-03 20:53:25 +02:00
Eddie Hung 5cd19b52da Merge remote-tracking branch 'origin/master' into xc7mux 2019-05-02 10:44:59 -07:00
Clifford Wolf 6bbe2fdbf3 Add splitcmplxassign test case and silence splitcmplxassign warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 10:01:54 +02:00
Clifford Wolf 3b6a02d3a7 Fix width detection of memory access with bit slice, fixes #974
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 09:57:26 +02:00
Clifford Wolf 59d74a3348 Re-enable "final loop assignment" feature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-05-01 09:02:39 +02:00
Clifford Wolf e35fe1344d Disabled "final loop assignment" feature
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 20:22:50 +02:00
Clifford Wolf 9c7d23446d
Merge pull request #972 from YosysHQ/clifford/fix968
Add final loop variable assignment when unrolling for-loops
2019-04-30 18:09:44 +02:00
Clifford Wolf 84f3a796e1 Include filename in "Executing Verilog-2005 frontend" message, fixes #959
Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-04-30 15:37:46 +02:00