mirror of https://github.com/YosysHQ/yosys.git
Parse "a" extension and boxes from map file
This commit is contained in:
Eddie Hung
parent
3f60061615
commit
3eec100748
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@ -192,8 +192,15 @@ void AigerReader::parse_xaiger()
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else
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log_abort();
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dict<int,IdString> box_lookup;
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for (auto m : design->modules()) {
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auto it = m->attributes.find("\\abc_box_id");
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if (it == m->attributes.end())
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continue;
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box_lookup[it->second.as_int()] = m->name;
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}
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// Parse footer (symbol table, comments, etc.)
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unsigned l1;
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std::string s;
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bool comment_seen = false;
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for (int c = f.peek(); c != EOF; c = f.peek()) {
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@ -247,7 +254,21 @@ void AigerReader::parse_xaiger()
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f >> s;
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log_debug("n: '%s'\n", s.c_str());
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}
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else if (c == 'a' || c == 'i' || c == 'o' || c == 'h') {
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else if (c == 'h') {
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f.ignore(sizeof(uint32_t));
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uint32_t version = parse_xaiger_literal(f);
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log_assert(version == 1);
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f.ignore(4*sizeof(uint32_t));
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uint32_t boxNum = parse_xaiger_literal(f);
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for (unsigned i = 0; i < boxNum; i++) {
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f.ignore(2*sizeof(uint32_t));
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uint32_t boxUniqueId = parse_xaiger_literal(f);
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log_assert(boxUniqueId > 0);
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uint32_t oldBoxNum = parse_xaiger_literal(f);
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module->addCell(stringf("$__box%u__", oldBoxNum), box_lookup.at(boxUniqueId));
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}
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}
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else if (c == 'a' || c == 'i' || c == 'o') {
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uint32_t dataSize = parse_xaiger_literal(f);
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f.ignore(dataSize);
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}
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@ -471,7 +492,7 @@ void AigerReader::parse_aiger_binary()
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log_debug("%d is an output\n", l1);
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const unsigned variable = l1 >> 1;
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const bool invert = l1 & 1;
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RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "_inv" the right suffix?
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RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "_b" the right suffix?
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wire = module->wire(wire_name);
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if (!wire)
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wire = createWireIfNotExists(module, l1);
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@ -527,6 +548,7 @@ void AigerReader::post_process()
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std::ifstream mf(map_filename);
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std::string type, symbol;
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int variable, index;
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int pi_count = 0, ci_count = 0, co_count = 0;
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while (mf >> type >> variable >> index >> symbol) {
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RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
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if (type == "input") {
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@ -534,6 +556,7 @@ void AigerReader::post_process()
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RTLIL::Wire* wire = inputs[variable];
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log_assert(wire);
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log_assert(wire->port_input);
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pi_count++;
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if (index == 0) {
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// Cope with the fact that a CI might be identical
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@ -562,8 +585,8 @@ void AigerReader::post_process()
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}
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}
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else if (type == "output") {
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log_assert(static_cast<unsigned>(variable) < outputs.size());
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RTLIL::Wire* wire = outputs[variable];
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log_assert(static_cast<unsigned>(variable + co_count) < outputs.size());
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RTLIL::Wire* wire = outputs[variable + co_count];
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log_assert(wire);
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log_assert(wire->port_output);
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if (escaped_s.in("\\__dummy_o__", "\\__const0__", "\\__const1__")) {
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@ -617,42 +640,38 @@ void AigerReader::post_process()
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}
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}
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}
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else if (type == "cinput" || type == "coutput") {
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RTLIL::Wire* wire;
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if (type == "cinput") {
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log_assert(static_cast<unsigned>(variable) < inputs.size());
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wire = inputs[variable];
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log_assert(wire);
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log_assert(wire->port_input);
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}
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else if (type == "coutput") {
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log_assert(static_cast<unsigned>(variable) < outputs.size());
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wire = outputs[variable];
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log_assert(wire);
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log_assert(wire->port_output);
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}
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else log_abort();
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std::string port, type;
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mf >> port >> type;
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RTLIL::IdString cell_name = RTLIL::escape_id(symbol);
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RTLIL::IdString cell_port = RTLIL::escape_id(port);
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RTLIL::IdString cell_type = RTLIL::escape_id(type);
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RTLIL::Cell* cell = module->cell(cell_name);
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if (!cell)
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cell = module->addCell(cell_name, cell_type);
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else
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log_assert(cell->type == cell_type);
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wire->port_input = false;
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wire->port_output = false;
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if (cell->hasPort(cell_port)) {
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log_assert(index == GetSize(cell->getPort(cell_port)));
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cell->connections_[cell_port].append(wire);
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}
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else {
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log_assert(index == 0);
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cell->setPort(cell_port, wire);
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else if (type == "box") {
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RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable));
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if (cell) {
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module->rename(cell, escaped_s);
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RTLIL::Module* box_module = design->module(cell->type);
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log_assert(box_module);
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// NB: Assume box_module->ports are sorted alphabetically
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// (as RTLIL::Module::fixup_ports() would do)
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for (auto port_name : box_module->ports) {
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RTLIL::Wire* w = box_module->wire(port_name);
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log_assert(w);
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RTLIL::SigSpec rhs;
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for (int i = 0; i < GetSize(w); i++) {
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if (w->port_input) {
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log_assert(static_cast<unsigned>(co_count) < outputs.size());
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RTLIL::Wire* wire = outputs[co_count++];
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log_assert(wire);
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log_assert(wire->port_output);
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wire->port_output = false;
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rhs.append(wire);
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}
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if (w->port_output) {
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log_assert(static_cast<unsigned>(pi_count + ci_count) < inputs.size());
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RTLIL::Wire* wire = inputs[pi_count + ci_count++];
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log_assert(wire);
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log_assert(wire->port_input);
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wire->port_input = false;
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rhs.append(wire);
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}
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}
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cell->setPort(port_name, rhs);
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}
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}
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}
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else
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