644e55b3d3
Replace `std::map` with `dict` for `celltypeMap`.
2020-05-14 20:06:53 +00:00
67f4046c05
Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`.
2020-05-14 20:06:53 +00:00
64c16f8c13
Replace `std::map` with `dict` for `positional_ports`.
2020-05-14 20:06:53 +00:00
2fb4931e5b
Add specialized `hash()` for type `dict` and use a `dict` instead of a `std::map` for `techmap_cache` and `techmap_do_cache`.
2020-05-14 20:06:53 +00:00
437f3fb342
Replace `std::map` with `dict` for `simplemap_mappers`.
2020-05-14 20:06:53 +00:00
99b586b283
Use `nullptr` instead of `NULL` in `passes/techmap/techmap.cc`.
2020-05-14 20:06:53 +00:00
5f7f213c7f
Replace `std::string` and `RTLIL::IdString` with `IdString` in `passes/techmap/techmap.cc`.
...
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:53 +00:00
e49fdee404
Do not modify design modules while iterating over `modules()`.
...
Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
2020-05-14 20:06:53 +00:00
985a29ff3b
Clean up pseudo-private member usage, superfluous `std::vector` instantiation, and `RTLIL::id2cstr()` usage in `passes/techmap/techmap.cc`.
2020-05-14 20:06:53 +00:00
283b1130a6
Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup
...
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-05 07:59:40 -07:00
ae409d4d81
Merge pull request #2012 from whitequark/fix-wasi-abc-build
...
Fix WASI builds with abc enabled
2020-05-05 14:03:40 +00:00
5fa06e4894
Merge pull request #2026 from YosysHQ/eddie/scratchpad_abc9_W
...
synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
2020-05-05 06:49:36 -07:00
7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src
...
verilog: set src attribute for primitives
2020-05-05 06:49:18 -07:00
99aff5a0f9
Merge pull request #2023 from YosysHQ/eddie/specify_src
...
verilog: fix specify src attribute
2020-05-05 06:49:06 -07:00
e6b55e8b38
synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
2020-05-04 11:44:00 -07:00
eb5eb60fd4
verilog: fix specify src attribute
2020-05-04 10:53:06 -07:00
22bf22fab4
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-04 10:48:37 -07:00
eca9fc01a7
verilog: set src attribute for primitives
2020-05-04 10:22:05 -07:00
ad8e7878f6
tests: add tests for primitives' src
2020-05-04 10:21:47 -07:00
584780d776
Merge pull request #1996 from boqwxp/rtlil_source_locations
...
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-04 08:58:50 -07:00
d1c8837572
Merge pull request #2000 from whitequark/log_error-trap
...
kernel: Trap in `log_error()` when a debugger is attached
2020-05-03 16:19:42 +00:00
e9f2d3f009
kernel: Trap in `log_error()` when a debugger is attached.
...
The workflow of debugging fatal pass errors in Yosys is flawed in
three ways:
1. Running Yosys under a debugger is sufficient for the debugger
to catch some fatal errors (segfaults, aborts, STL exceptions)
but not others (`log_error()`, `log_cmd_error()`). This is
neither obvious nor easy to remember.
2. To catch Yosys-specific fatal errors, it is necessary to set
a breakpoint at `logv_error_with_prefix()`, or at least,
`logv_error()`. This is neither obvious nor easy to remember,
and GDB's autocomplete takes many seconds to suggest function
names due to the large amount of symbols in Yosys.
3. If a breakpoint is not set and Yosys encounters with such
a fatal error, the process terminates. When debugging a crash
that takes a long time to reproduce (or a nondeterministic crash)
this can waste a significant amount of time.
To solve this problem, add a macro `YS_DEBUGTRAP` that acts as a hard
breakpoint (if available), and a macro `YS_DEBUGTRAP_IF_DEBUGGING`
that acts as a hard breakpoint only if debugger is present.
Then, use `YS_DEBUGTRAP_IF_DEBUGGING` in `logv_error_with_prefix()`
to obviate the need for a breakpoint on nearly every platform.
Co-Authored-By: Alberto Gonzalez <boqwxp@airmail.cc>
2020-05-03 12:02:34 +00:00
5c82c19b4b
Merge pull request #2014 from YosysHQ/claire/fixoptalu
...
Fix the other "opt_expr -fine" bug introduced in 213a89558
2020-05-03 11:56:29 +02:00
db13852ed6
test: add test for #2014
2020-05-02 14:22:37 -07:00
7360155459
Merge pull request #2013 from YosysHQ/eddie/aiger_fixes
...
aiger: fixes for ports that have start_offset != 0
2020-05-02 14:16:10 -07:00
2285cf1219
Fix the other "opt_expr -fine" bug introduced in 213a89558
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 21:50:43 +02:00
da7da44919
abc9_ops: -reintegrate to be sensitive to start_offset too
2020-05-02 11:19:04 -07:00
2e78daf1ca
tests: aiger test for wire->start_offset != 0
2020-05-02 10:00:32 -07:00
a0afa1787e
aiger: fixes for ports that have start_offset != 0
2020-05-02 10:00:32 -07:00
ca3fc3c882
Merge pull request #2010 from YosysHQ/claire/fixopt
...
Fix "opt_expr -fine" bug introduced in 213a89558
2020-05-02 11:20:02 +02:00
ff7a8d0e1e
Update ABC to include WASI support fixes.
2020-05-02 00:18:33 +00:00
b36060cc20
Fix WASI builds with abc enabled.
...
This PR works around #2011 .
2020-05-01 23:57:35 +00:00
bbde241942
Merge pull request #2001 from whitequark/wasi
...
Add WASI platform support
2020-05-01 21:28:20 +00:00
7f9ecddb7f
Add testcase for #2010
2020-05-01 14:07:33 -07:00
8ee32adac3
Fix "opt_expr -fine" bug introduced in 213a89558
...
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-01 20:12:16 +02:00
667f38fe53
Merge pull request #1997 from whitequark/document-ootb
...
Explain how to do out-of-tree builds in README
2020-05-01 15:35:33 +02:00
d047ca8b11
Merge pull request #1981 from YosysHQ/claire/fix1837
...
Clear current_scope when done with RTLIL generation
2020-05-01 14:58:41 +02:00
b0268b1311
frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-01 07:17:27 +00:00
b43c282e4e
Add WASI platform support.
...
This includes the following significant changes:
* Patching ezsat and minisat to disable resource limiting code
on WASM/WASI, since the POSIX functions they use are unavailable.
* Adding a new definition, YOSYS_DISABLE_SPAWN, present if platform
does not support spawning subprocesses (i.e. Emscripten or WASI).
This definition hides the definition of `run_command()`.
* Adding a new Makefile flag, DISABLE_SPAWN, present in the same
condition. This flag disables all passes that require spawning
subprocesses for their function.
2020-04-30 18:56:25 +00:00
bc380b0b56
Merge pull request #1999 from YosysHQ/eddie/verific_enum_again
...
verific: recover wiretype/enum attr as part of import_attributes()
2020-04-30 09:07:02 -07:00
33c9c04561
Merge pull request #2008 from whitequark/editorconfig-abc
...
Fix .editorconfig to not break abc
2020-04-30 15:53:27 +00:00
5017ff4a97
verific: ignore anonymous enums
2020-04-30 07:48:47 -07:00
adeed6f730
Fix .editorconfig to not break abc.
2020-04-30 02:22:37 +00:00
97bfe65d3a
verific: support VHDL enums too
2020-04-27 15:17:13 -07:00
a66200ed1d
Merge pull request #1946 from YosysHQ/eddie/yosyshq_abc
...
abc: use YosysHQ/abc instead of upstream berkeley-abc/abc
2020-04-27 13:48:50 -07:00
c34d57de2e
Update CHANGELOG and manual for departure from upstream
2020-04-27 12:08:45 -07:00
a3fa9fd6e9
abc: use YosysHQ/abc instead of upstream berkeley-abc/abc
...
Enabling modifications
2020-04-27 12:03:40 -07:00
eabc00de8b
Merge pull request #1992 from YosysHQ/eddie/bugpoint_help
...
bugpoint: improve help text
2020-04-27 11:12:17 -07:00
dd5f206d9e
verific: recover wiretype/enum attr as part of import_attributes()
2020-04-27 08:43:54 -07:00
868b6b1b0d
Merge pull request #2002 from YosysHQ/dave/cxxrtl-width
...
cxxrtl: Round up constant width
2020-04-25 18:30:53 +00:00
Alberto Gonzalez
Eddie Hung
whitequark
Claire Wolf
Claire Wolf