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Merge pull request #1999 from YosysHQ/eddie/verific_enum_again 

verific: recover wiretype/enum attr as part of import_attributes()
This commit is contained in:
Eddie Hung 2020-04-30 09:07:02 -07:00 committed by GitHub
parent 33c9c04561 5017ff4a97
commit bc380b0b56
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 68 additions and 30 deletions
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96
frontends/verific/verific.cc
View File

@ -149,7 +149,7 @@ RTLIL::IdString VerificImporter::new_verific_id(Verific::DesignObj *obj)
return s;
}
void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj)
void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj, Netlist *nl)
{
MapIter mi;
Att *attr;
@ -163,6 +163,68 @@ void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &att
continue;
attributes[RTLIL::escape_id(attr->Key())] = RTLIL::Const(std::string(attr->Value()));
}
if (nl) {
auto type_range = nl->GetTypeRange(obj->Name());
if (!type_range)
return;
if (!type_range->IsTypeEnum())
return;
if (nl->IsFromVhdl() && strcmp(type_range->GetTypeName(), "STD_LOGIC") == 0)
return;
auto type_name = type_range->GetTypeName();
if (!type_name)
return;
attributes.emplace(ID::wiretype, RTLIL::escape_id(type_name));
MapIter mi;
const char *k, *v;
FOREACH_MAP_ITEM(type_range->GetEnumIdMap(), mi, &k, &v) {
if (nl->IsFromVerilog()) {
// Expect <decimal>'b<binary>
auto p = strchr(v, '\'');
if (p) {
if (*(p+1) != 'b')
p = nullptr;
else
for (auto q = p+2; *q != '\0'; q++)
if (*q != '0' && *q != '1') {
p = nullptr;
break;
}
}
if (p == nullptr)
log_error("Expected TypeRange value '%s' to be of form <decimal>'b<binary>.\n", v);
attributes.emplace(stringf("\\enum_value_%s", p+2), RTLIL::escape_id(k));
}
else if (nl->IsFromVhdl()) {
// Expect "<binary>"
auto p = v;
if (p) {
if (*p != '"')
p = nullptr;
else {
auto *q = p+1;
for (; *q != '"'; q++)
if (*q != '0' && *q != '1') {
p = nullptr;
break;
}
if (p && *(q+1) != '\0')
p = nullptr;
}
}
if (p == nullptr)
log_error("Expected TypeRange value '%s' to be of form \"<binary>\".\n", v);
auto l = strlen(p);
auto q = (char*)malloc(l+1-2);
strncpy(q, p+1, l-2);
q[l-2] = '\0';
attributes.emplace(stringf("\\enum_value_%s", q), RTLIL::escape_id(k));
free(q);
}
}
}
}
RTLIL::SigSpec VerificImporter::operatorInput(Instance *inst)
@ -845,7 +907,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
log(" importing port %s.\n", port->Name());
RTLIL::Wire *wire = module->addWire(RTLIL::escape_id(port->Name()));
import_attributes(wire->attributes, port);
import_attributes(wire->attributes, port, nl);
wire->port_id = nl->IndexOf(port) + 1;
@ -872,7 +934,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
RTLIL::Wire *wire = module->addWire(RTLIL::escape_id(portbus->Name()), portbus->Size());
wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex());
import_attributes(wire->attributes, portbus);
import_attributes(wire->attributes, portbus, nl);
if (portbus->GetDir() == DIR_INOUT || portbus->GetDir() == DIR_IN)
wire->port_input = true;
@ -1021,7 +1083,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
log(" importing net %s as %s.\n", net->Name(), log_id(wire_name));
RTLIL::Wire *wire = module->addWire(wire_name);
import_attributes(wire->attributes, net);
import_attributes(wire->attributes, net, nl);
net_map[net] = wire;
}
@ -1046,7 +1108,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
RTLIL::Wire *wire = module->addWire(wire_name, netbus->Size());
wire->start_offset = min(netbus->LeftIndex(), netbus->RightIndex());
import_attributes(wire->attributes, netbus);
import_attributes(wire->attributes, netbus, nl);
RTLIL::Const initval = Const(State::Sx, GetSize(wire));
bool initval_valid = false;
@ -1153,30 +1215,6 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
for (auto net : anyseq_nets)
module->connect(net_map_at(net), module->Anyseq(new_verific_id(net)));
char *id_name;
TypeRange *type_range;
FOREACH_MAP_ITEM(nl->GetTypeRangeTable(), mi, &id_name, &type_range)
{
if (!type_range)
continue;
if (!type_range->IsTypeEnum())
continue;
auto wire = module->wire(RTLIL::escape_id(id_name));
if (!wire) {
if (net->IsUserDeclared())
log_warning("Unable to find imported net '%s'.\n", net->Name());
continue;
}
wire->set_string_attribute(ID::wiretype, type_range->GetTypeName());
MapIter mj;
char *k, *v;
FOREACH_MAP_ITEM(type_range->GetEnumIdMap(), mj, &k, &v) {
IdString key = stringf("\\enum_value_%s", v);
wire->set_string_attribute(key, k);
}
}
pool<Instance*, hash_ptr_ops> sva_asserts;
pool<Instance*, hash_ptr_ops> sva_assumes;
pool<Instance*, hash_ptr_ops> sva_covers;

2
frontends/verific/verific.h
View File

@ -79,7 +79,7 @@ struct VerificImporter
RTLIL::SigBit net_map_at(Verific::Net *net);
RTLIL::IdString new_verific_id(Verific::DesignObj *obj);
void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, Verific::DesignObj *obj);
void import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, Verific::DesignObj *obj, Verific::Netlist *nl = nullptr);
RTLIL::SigSpec operatorInput(Verific::Instance *inst);
RTLIL::SigSpec operatorInput1(Verific::Instance *inst);