mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1946 from YosysHQ/eddie/yosyshq_abc
abc: use YosysHQ/abc instead of upstream berkeley-abc/abc
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commit
a66200ed1d
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@ -8,7 +8,7 @@ Yosys 0.9 .. Yosys 0.9-dev
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* Various
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- Added "write_xaiger" backend
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- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
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- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only)
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- Added "synth_xilinx -abc9" (experimental)
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- Added "synth_ice40 -abc9" (experimental)
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- Added "synth -abc9" (experimental)
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@ -58,7 +58,6 @@ Yosys 0.9 .. Yosys 0.9-dev
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- Added support for SystemVerilog wildcard port connections (.*)
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- Added "xilinx_dffopt" pass
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- Added "scratchpad" pass
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- Added "abc9 -dff"
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- Added "synth_xilinx -dff"
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- Improved support of $readmem[hb] Memory Content File inclusion
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- Added "opt_lut_ins" pass
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@ -66,6 +65,7 @@ Yosys 0.9 .. Yosys 0.9-dev
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- Removed "dffsr2dff" (use opt_rmdff instead)
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- Added "design -delete"
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- Added "select -unset"
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- Use YosysHQ/abc instead of upstream berkeley-abc/abc
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Yosys 0.8 .. Yosys 0.9
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----------------------
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4
Makefile
4
Makefile
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@ -133,9 +133,9 @@ bumpversion:
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# is just a symlink to your actual ABC working directory, as 'make mrproper'
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# will remove the 'abc' directory and you do not want to accidentally
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# delete your work on ABC..
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ABCREV = ed90ce2
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ABCREV = d14acd8
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ABCPULL = 1
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ABCURL ?= https://github.com/berkeley-abc/abc
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ABCURL ?= https://github.com/YosysHQ/abc
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ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1
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# set ABCEXTERNAL = <abc-command> to use an external ABC instance
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@ -19,7 +19,8 @@ for details.
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\section{yosys-abc}
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This is a unmodified copy of ABC \citeweblink{ABC}. Not all versions of Yosys
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work with all versions of ABC. So Yosys comes with its own yosys-abc to avoid
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This is a fork of ABC \citeweblink{ABC} with a small set of custom modifications
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that have not yet been accepted upstream. Not all versions of Yosys work with
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all versions of ABC. So Yosys comes with its own yosys-abc to avoid
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compatibility issues between the two.
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