237962debd
verilog: default to input in sv mode if task/func has no dir ...
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otherwise error
2020-05-13 13:33:37 -07:00
0d2c33f9f4
tests: update/extend task argument tests
2020-05-13 10:11:45 -07:00
27b7ffc754
ice40: fix ICESTORM_LC process sensitivity
2020-05-12 15:40:48 -07:00
4ecae8a673
ice40: fix whitespace
2020-05-12 15:40:13 -07:00
95fb3cf487
ecp5: Add missing SERDES parameters
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Signed-off-by: David Shah <dave@ds0.me>
2020-05-12 21:12:26 +01:00
1f3003be7d
verilog: error out when non-ANSI task/func arguments
2020-05-11 13:00:36 -07:00
e5ce5a4fd5
tests: add #2042 testcase
2020-05-11 11:05:19 -07:00
b11cf67a81
Setup tests/verilog properly
2020-05-11 10:31:02 -07:00
aafaeb66df
Merge pull request #2038 from nakengelhardt/no-libdir-flag
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Remove yosys libdir from LDFLAGS (and fix a typo)
2020-05-08 10:40:25 +02:00
8ec3b6db1c
Fix clang compiler warning
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-08 10:13:39 +02:00
ebfdf61eb9
Merge pull request #2022 from Xiretza/fallthroughs
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Avoid switch fall-through warnings
2020-05-08 05:30:32 +00:00
5b779f7f4e
intel_alm: direct LUTRAM cell instantiation
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By instantiating the LUTRAM cell directly, we avoid a trip through
altsyncram, which speeds up Quartus synthesis time. This also gives
a little more flexibility, as Yosys can build RAMs out of individual
32x1 LUTRAM cells.
While working on this, I discovered that the mem_init0 parameter of
<family>_mlab_cell gets ignored by Quartus.
2020-05-07 21:03:13 +02:00
c9befa769f
Remove yosys libdir from LDFLAGS (and fix a typo)
2020-05-07 19:28:18 +02:00
0610424940
Merge pull request #2005 from YosysHQ/claire/fix1990
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Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset
2020-05-07 18:11:48 +02:00
3a985d8285
Merge pull request #2034 from YosysHQ/eddie/abc_remote
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Makefile: git fetch $(ABCURL) explicitly for local ABC checkout
2020-05-07 08:07:42 -07:00
d86fc791f9
Reorder cases to avoid fall-through warning
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log_assert(false) never returns and thus can't fall through, but gcc
doesn't seem to think that far. Making it the last case avoids the
problem entirely.
2020-05-07 13:39:34 +02:00
695150b037
Add YS_FALLTHROUGH macro to mark case fall-through
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C++17 introduced [[fallthrough]], GCC and clang had their own vendored
attributes before that. MSVC doesn't seem to have such a warning at all.
2020-05-07 13:39:34 +02:00
8eb98b12c7
Makefile: git fetch all commits from $(ABCURL) repo
2020-05-06 16:23:46 -07:00
a299e606f8
Merge pull request #2028 from zachjs/master
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verilog: allow null gen-if then block
2020-05-06 12:10:28 -07:00
8f9bba1bbf
verilog: allow null gen-if then block
2020-05-06 08:43:02 -04:00
004999218f
techlibs/common: more robustness when *_WIDTH = 0
2020-05-05 08:01:27 -07:00
283b1130a6
Merge pull request #2025 from YosysHQ/eddie/frontend_cleanup
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frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-05 07:59:40 -07:00
ae409d4d81
Merge pull request #2012 from whitequark/fix-wasi-abc-build
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Fix WASI builds with abc enabled
2020-05-05 14:03:40 +00:00
5fa06e4894
Merge pull request #2026 from YosysHQ/eddie/scratchpad_abc9_W
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synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
2020-05-05 06:49:36 -07:00
7a62ee57b4
Merge pull request #2024 from YosysHQ/eddie/primitive_src
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verilog: set src attribute for primitives
2020-05-05 06:49:18 -07:00
99aff5a0f9
Merge pull request #2023 from YosysHQ/eddie/specify_src
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verilog: fix specify src attribute
2020-05-05 06:49:06 -07:00
e936ac61ea
ast: swap range regardless of range_left >= 0
2020-05-04 12:18:20 -07:00
2e911bc806
test: add failing test
2020-05-04 12:18:02 -07:00
e6b55e8b38
synth_ice40/ecp5/xilinx: allow abc9.W to be overridden via scratchpad
2020-05-04 11:44:00 -07:00
eb5eb60fd4
verilog: fix specify src attribute
2020-05-04 10:53:06 -07:00
22bf22fab4
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-04 10:48:37 -07:00
eca9fc01a7
verilog: set src attribute for primitives
2020-05-04 10:22:05 -07:00
ad8e7878f6
tests: add tests for primitives' src
2020-05-04 10:21:47 -07:00
584780d776
Merge pull request #1996 from boqwxp/rtlil_source_locations
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frontend: Include complete source location instead of just `location.first_line` in `frontends/ast/genrtlil.cc`.
2020-05-04 08:58:50 -07:00
d1c8837572
Merge pull request #2000 from whitequark/log_error-trap
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kernel: Trap in `log_error()` when a debugger is attached
2020-05-03 16:19:42 +00:00
e9f2d3f009
kernel: Trap in `log_error()` when a debugger is attached.
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The workflow of debugging fatal pass errors in Yosys is flawed in
three ways:
1. Running Yosys under a debugger is sufficient for the debugger
to catch some fatal errors (segfaults, aborts, STL exceptions)
but not others (`log_error()`, `log_cmd_error()`). This is
neither obvious nor easy to remember.
2. To catch Yosys-specific fatal errors, it is necessary to set
a breakpoint at `logv_error_with_prefix()`, or at least,
`logv_error()`. This is neither obvious nor easy to remember,
and GDB's autocomplete takes many seconds to suggest function
names due to the large amount of symbols in Yosys.
3. If a breakpoint is not set and Yosys encounters with such
a fatal error, the process terminates. When debugging a crash
that takes a long time to reproduce (or a nondeterministic crash)
this can waste a significant amount of time.
To solve this problem, add a macro `YS_DEBUGTRAP` that acts as a hard
breakpoint (if available), and a macro `YS_DEBUGTRAP_IF_DEBUGGING`
that acts as a hard breakpoint only if debugger is present.
Then, use `YS_DEBUGTRAP_IF_DEBUGGING` in `logv_error_with_prefix()`
to obviate the need for a breakpoint on nearly every platform.
Co-Authored-By: Alberto Gonzalez <boqwxp@airmail.cc>
2020-05-03 12:02:34 +00:00
5c82c19b4b
Merge pull request #2014 from YosysHQ/claire/fixoptalu
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Fix the other "opt_expr -fine" bug introduced in 213a89558
2020-05-03 11:56:29 +02:00
db13852ed6
test: add test for #2014
2020-05-02 14:22:37 -07:00
7360155459
Merge pull request #2013 from YosysHQ/eddie/aiger_fixes
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aiger: fixes for ports that have start_offset != 0
2020-05-02 14:16:10 -07:00
2285cf1219
Fix the other "opt_expr -fine" bug introduced in 213a89558
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 21:50:43 +02:00
885deb4e88
Fix the other "opt_expr -fine" bug introduced in 213a89558
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 21:34:24 +02:00
da7da44919
abc9_ops: -reintegrate to be sensitive to start_offset too
2020-05-02 11:19:04 -07:00
2e78daf1ca
tests: aiger test for wire->start_offset != 0
2020-05-02 10:00:32 -07:00
a0afa1787e
aiger: fixes for ports that have start_offset != 0
2020-05-02 10:00:32 -07:00
c3e5a070ea
Add plusargs for output files in test_autotb output
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
f38d76efbf
Bugfix in partsel.v signed indices test cases
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
88185f8959
Fix handling of signed indices in bit slices
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
749c2ff84a
Add tests based on the test case from #1990
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
589ed2d970
Add AST_SELFSZ and improve handling of bit slices
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
bbbce0d1c5
Add "nowrshmsk" attribute, fix shift-and-mask bit slice write for signed offset, fixes #1990
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Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-05-02 11:21:01 +02:00
Eddie Hung
David Shah
Claire Wolf
Claire Wolf
whitequark
Dan Ravensloft
N. Engelhardt
Xiretza
Zachary Snow