Eddie Hung
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dd134914cc
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Error out if no top module given before 'sim'
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2019-06-05 14:16:24 -07:00 |
Eddie Hung
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feb2ddb52b
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Fix typo in opt_rmdff
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2019-06-05 14:08:14 -07:00 |
Eddie Hung
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935df3569b
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shregmap -tech xilinx_static to handle INIT
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2019-06-05 12:55:59 -07:00 |
Eddie Hung
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72eda94a66
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Continue support for ShregmapTechXilinx7Static
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2019-06-05 12:33:55 -07:00 |
Eddie Hung
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6ed15b7890
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Update abc attributes on FD*E_1
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2019-06-05 12:33:40 -07:00 |
Eddie Hung
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67f744d428
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Cleanup
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2019-06-05 12:28:46 -07:00 |
Eddie Hung
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2c18d530ea
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Call shregmap -tech xilinx_static
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2019-06-05 12:28:26 -07:00 |
Eddie Hung
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e473e74565
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Revert "Move ff_map back after ABC for shregmap"
This reverts commit 9b9bd4e19f .
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2019-06-05 11:53:06 -07:00 |
Eddie Hung
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dfe9d95579
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Add -tech xilinx_static
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2019-06-05 11:14:14 -07:00 |
Eddie Hung
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e1e37db860
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Refactor to ShregmapTechXilinx7Static
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2019-06-05 11:08:08 -07:00 |
Eddie Hung
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45d1bdf83a
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shregmap -tech xilinx_dynamic to work -params and -enpol
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2019-06-05 10:21:57 -07:00 |
Eddie Hung
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a3a80b755c
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Merge pull request #1067 from YosysHQ/clifford/fix1065
Suppress driver-driver conflict warning for unknown cell types
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2019-06-05 09:59:05 -07:00 |
Eddie Hung
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bcc0a5d136
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Merge remote-tracking branch 'origin/master' into xc7mux
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2019-06-05 09:56:57 -07:00 |
Eddie Hung
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b5aff1de04
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Merge remote-tracking branch 'origin/clifford/fix1065' into xc7mux
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2019-06-05 09:56:51 -07:00 |
Maciej Kurc
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03e0d3a17c
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Fixed memory leak.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2019-06-05 10:42:43 +02:00 |
Clifford Wolf
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f15b5e6309
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Merge pull request #1066 from YosysHQ/clifford/fix1056
Remove yosys_banner() from python wrapper init
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2019-06-05 10:37:39 +02:00 |
Clifford Wolf
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b33176dafb
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Major rewrite of wire selection in setundef -init
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-05 10:26:48 +02:00 |
Clifford Wolf
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6cc60ffd67
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Indent fix
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-05 09:53:06 +02:00 |
Clifford Wolf
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00d32eb73d
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Merge pull request #999 from jakobwenzel/setundefInitFix
initialize more registers in setundef -init
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2019-06-05 09:50:15 +02:00 |
Clifford Wolf
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4190d7c094
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Fix typo in fmcombine log message, fixes #1063
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-05 09:26:44 +02:00 |
Clifford Wolf
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8a6f9977f6
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Suppress driver-driver conflict warning for unknown cell types, fixes #1065
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-05 09:14:12 +02:00 |
Clifford Wolf
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dd3c333c0a
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Remove yosys_banner() from python wrapper init, fixes #1056
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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2019-06-05 08:57:33 +02:00 |
Eddie Hung
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94a5f4e609
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Rename shregmap -tech xilinx -> xilinx_dynamic
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2019-06-04 14:34:36 -07:00 |
Eddie Hung
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7b186740d3
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Add log_assert to ensure no loops
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2019-06-04 12:01:25 -07:00 |
Eddie Hung
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1b836c93bb
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Only toposort builtin and abc types
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2019-06-04 11:56:58 -07:00 |
Eddie Hung
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82d41bc2f2
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Add space between -D and _ABC
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2019-06-04 11:54:08 -07:00 |
Eddie Hung
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f0e93f33cf
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Add (* abc_flop_q *) to brams_bb.v
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2019-06-04 11:53:51 -07:00 |
Eddie Hung
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6cf092641f
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Fix name clash
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2019-06-04 09:56:36 -07:00 |
Eddie Hung
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e260150321
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Add mux_map.v for wide mux
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2019-06-04 09:51:47 -07:00 |
Clifford Wolf
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1332051f33
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Merge pull request #1062 from tux3/patch-1
README.md: Missing formatting for <tag>
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2019-06-04 14:37:10 +02:00 |
Tux3
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c66d644b66
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README.md: Missing formatting for <tag>
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2019-06-04 10:45:41 +02:00 |
Maciej Kurc
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b79bd5b3ca
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Moved tests that fail with Icarus Verilog to /tests/various. Those tests are just for parsing Verilog.
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
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2019-06-04 10:42:42 +02:00 |
Eddie Hung
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9b9bd4e19f
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Move ff_map back after ABC for shregmap
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2019-06-03 23:43:23 -07:00 |
Eddie Hung
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09b778744d
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Respect -nocarry
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2019-06-03 23:42:30 -07:00 |
Eddie Hung
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5afa42432f
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Fix pmux2shiftx logic
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2019-06-03 23:29:45 -07:00 |
Eddie Hung
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23a73ca624
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Merge mistake
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2019-06-03 23:19:22 -07:00 |
Eddie Hung
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f81a0ed92e
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Merge remote-tracking branch 'origin/master' into xc7mux
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2019-06-03 23:07:08 -07:00 |
Eddie Hung
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1217e47e83
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Merge pull request #1061 from YosysHQ/eddie/techmap_and_arith_map
Execute techmap and arith_map simultaneously
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2019-06-03 20:23:37 -07:00 |
Eddie Hung
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b6e59741ae
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Typo
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2019-06-03 20:21:41 -07:00 |
Eddie Hung
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02973474df
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Remove extra newline
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2019-06-03 20:04:47 -07:00 |
Eddie Hung
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c9a0bac541
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IS_C_INVERTED
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2019-06-03 19:45:56 -07:00 |
Eddie Hung
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0ad50332d9
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Execute techmap and arith_map simultaneously
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2019-06-03 19:36:09 -07:00 |
Eddie Hung
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ebcc85b9b8
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Fix `ifndef
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2019-06-03 12:37:02 -07:00 |
Eddie Hung
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0092770317
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Make SB_LUT4 a whitebox, SB_DFF a blackbox (for now)
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2019-06-03 12:34:55 -07:00 |
Eddie Hung
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d018cd9fe3
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Assert that box_unique_id is indeed unique
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2019-06-03 12:33:47 -07:00 |
Eddie Hung
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295bd8d0bf
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Remove dupe
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2019-06-03 12:32:20 -07:00 |
Eddie Hung
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a54822b1bc
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Skip internal modules when generating box_unique_id
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2019-06-03 12:31:23 -07:00 |
Eddie Hung
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257f7ff5f6
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When creating new holes cell, inherit parameters too
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2019-06-03 12:30:54 -07:00 |
Eddie Hung
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4da25c76b3
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Ooopsie
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2019-06-03 09:33:42 -07:00 |
Eddie Hung
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9f44a71715
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Consistent with xilinx
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2019-06-03 09:23:43 -07:00 |