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3936 Commits

Author SHA1 Message Date
N. Engelhardt 3e22791810
Merge pull request #3975 from rmlarsen/optmerge 2023-10-09 17:05:19 +02:00
Martin Povišer 0434f9d3d1 booth: Fix vacancy check when summing down result 
In commit fedd12261 ("booth: Move away from explicit `Wire` pointers")
a bug was introduced when checking for vacant slots in arrays holding
some intermediate results. Non-wire SigBit values were taken to imply
a vacant slot, but actually a constant one can make its way into those
results, if the multiplier cell configuration is just right. Fix the
vacancy check to address the bug.
 2023-10-04 23:21:40 +02:00
Rasmus Munk Larsen 57a2b4b0cd Explicitly use uint64_t as the type of fingerprint to avoid type mismatch with some compilers. 2023-10-03 15:02:02 -07:00
Rasmus Munk Larsen 8e0308b5e7 Revert changes to celltypes.h. Use dict instead of std::unordered_map and most hash function for uint64_t to hashlib.h to support this. 2023-10-03 14:25:59 -07:00
Rasmus Munk Larsen bce984fa60 Speed up OptMergePass by 1.7x. 
The main speedup comes from swithing from using a SHA1 hash to std::hash<std::string>. There is no need to use an expensive cryptographic hash for fingerprinting in this context.
 2023-10-02 15:57:18 -07:00
Rasmus Munk Larsen 1bbc12f389 Revert changes to techmap.cc. 2023-10-02 17:32:56 +01:00
Rasmus Munk Larsen 67f1700486 Revert formatting changes. 2023-10-02 17:32:56 +01:00
Rasmus Munk Larsen abd9c51963 Speed up simplemap_map by 11.6x by directly inserting the cell source attribute in the new object's 'attributes' map instead of calling set_attr_pool to create a new pool and then copying that. Based on a suggestion by Martin Poviser in a comment on https://github.com/YosysHQ/yosys/pull/3959 2023-10-02 17:32:56 +01:00
Jannis Harder 8b42abee50
Merge pull request #3961 from jix/dft-fixes 2023-10-02 16:58:15 +02:00
Jannis Harder ecf09b9271
Merge pull request #3962 from jix/sim-noinitstate 2023-10-02 16:57:46 +02:00
N. Engelhardt dcb600ab81
Merge pull request #3938 from povik/booth-cleanup 2023-10-02 16:10:17 +02:00
Jannis Harder 5daa49bafb dft_tag: Fix size extending $x[n]or and $reduce_{or,bool}/$logic_not 2023-09-28 17:33:55 +02:00
Jannis Harder 7eaa4bcb46 sim: Add -noinitstate option and handle non-cosim initstate 
This adds the -noinitstate option which is required to simulate
counterexamples to induction with yw-cosim. Also add handling for
$initstate cells for non-co-simulation.
 2023-09-28 17:29:24 +02:00
Martin Povišer 6b70b3dbef booth: Fix assertion 
Fix assertion to what it should be per Andy's comments.
 2023-09-28 11:50:57 +02:00
N. Engelhardt 3319fdc46e show: use dot for wire aliases instead of BUF 2023-09-25 17:20:16 +02:00
Martin Povišer 91bcf81dbd booth: Note down debug prints are broken 2023-09-25 14:51:26 +02:00
Martin Povišer 7179e4f4b8 booth: Improve user interface 2023-09-25 14:50:41 +02:00
Martin Povišer cde2a0b926 booth: Make more use of appropriate helpers 
Use the `addFa` helper, do not misuse `new_id` and make other changes
to the transformation code.
 2023-09-25 14:50:41 +02:00
Martin Povišer 62302f601d booth: Remove more of unused helpers 2023-09-25 14:50:41 +02:00
Martin Povišer 30f8387b75 booth: Rewrite the main cell selection loop 2023-09-25 14:50:41 +02:00
Martin Povišer 986507f95f booth: Streamline the low-level circuit emission 
For the basic single-bit operations, opt for gate cells (`$_AND_` etc.)
instead of the coarse cells (`$and` etc.). For the emission of cells
move to the conventional module methods (`module->addAndGate`) away
from the local helpers. While at it, touch on the surrounding code.
 2023-09-25 14:50:41 +02:00
Martin Povišer cb05262fc4 booth: Remove now-unused helpers 2023-09-25 14:50:41 +02:00
Martin Povišer fedd12261f booth: Move away from explicit `Wire` pointers 
To represent intermediate signals use the `SigBit`/`SigSpec` classes as
is customary in the Yosys codebase. Do not pass around `Wire` pointers
unless we have special reason to.
 2023-09-25 14:50:41 +02:00
Rasmus Munk Larsen 9ed38bf9b6
Speed up the autoname pass by 3x. (#3945) 
* Speed up the autoname pass by 2x. This is accomplished by only constructing IdString objects for plain strings that have a higher score.

* Defer creating IdStrings even further. This increases the speedup to 3x.
 2023-09-21 09:46:49 +00:00
Martin Povišer 54be4aca90
Merge pull request #3924 from andyfox-rushc/master 
multpass -- create Booth Encoded multipliers for
 2023-09-18 16:46:59 +02:00
Jannis Harder 62b4df4989 dft_tag: Implement `$overwrite_tag` and `$original_tag` 
This does not correctly handle an `$overwrite_tag` on a module output,
but since we currently require the user to flatten the design for
cross-module dft, this cannot be observed from within the design, only
by manually inspecting the signals in the design.
 2023-09-13 11:32:36 +02:00
Jannis Harder 46a35da28c Add `future` pass to resolve `$future_ff` cells 2023-09-13 11:32:36 +02:00
Jannis Harder 7a0c37b62d Initial dft_tag implementation 
This is still missing a mode to rewrite $overwrite_tag and $original_tag
by injecting $set_tag and $get_tag in the right places. It's also
missing bit-precise propagation models for shifts and arithmetic and
requires the design to be flattened.
 2023-09-13 11:32:36 +02:00
Miodrag Milanović 88ce47e4f0
Merge pull request #3892 from QuantamHD/dont_use 
abc: Exposes dont_use flag in ABC
 2023-09-12 14:58:44 +02:00
andyfox-rushc e4fe522767 MultPassWorker -> BoothPassWorker 2023-09-11 13:00:11 -07:00
andyfox-rushc eccc0ae6db Based passes/techmap/Makefile.inc changes on latest in yosys 2023-09-11 12:14:12 -07:00
andyfox-rushc a2c8e47295 multpass.cc -> booth.cc, added author/support contact info 2023-09-11 11:39:13 -07:00
Martin Povišer 5bef9b4e75
Merge pull request #3915 from povik/sim-print 
sim: Add print support
 2023-09-11 17:03:59 +02:00
andyfox-rushc 1b5287af59 cpa_carry array added to heap 2023-09-10 14:20:30 -07:00
andyfox-rushc 8d4b6c2f69 Switched arrays for signed multiplier construction to heap 2023-09-10 13:31:47 -07:00
andyfox-rushc d77fb81507 2d array -> 1d array in module generator 2023-09-10 12:45:36 -07:00
andyfox-rushc 6d29dc659b renamed passname to booth, replaced connect_sigSpecToWire with connect, updated test script 2023-09-08 15:34:56 -07:00
andyfox-rushc 411acc4a0a Fixed edge size cases for signed/unsigned booth generator 2023-09-08 13:41:31 -07:00
andyfox-rushc fedefa26bc multpass -- create Booth Encoded multipliers for 2023-09-06 16:35:17 -07:00
Jannis Harder e187fc915e xprop: Fix polarity errors and generate hdlnames 
* Fixes a non-deterministic polarity error for $eqx/$nex cells
* Fixes a deterministic polarity error for $_NOR_ and $_ORNOT_ cells
* Generates hdlnames when xprop is run after flatten
 2023-09-06 19:25:47 +02:00
Martin Povišer d4d951657f sim: Add `-assert` option to fail on failed assertions 2023-09-05 10:46:04 +02:00
Martin Povišer e995dddeaa abc: Warn about replacing undef bits 2023-09-05 10:45:30 +02:00
Martin Povišer c6566b660f memlib.md: Fix typo 2023-09-04 17:38:35 +02:00
Martin Povišer 3de84b959f memory_libmap: Tweak whitespace 2023-09-04 17:38:35 +02:00
Martin Povišer 50d117956c sim: Add print support 2023-09-04 17:12:38 +02:00
Miodrag Milanovic a8809989c4 ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech 2023-08-22 10:50:11 +02:00
Ethan Mahintorabi d525a41497
abc: Exposes dont_use flag in ABC 
ABC's read_lib command has a dont_use
cell list that is configurable by the user.

This PR exposes that option to Yosys.

See
5405d4787a/src/map/scl/scl.c (L285)
for documentation on this option.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2023-08-15 20:03:46 +00:00
Charlotte 860e3e4056 proc_clean: only consider fully-defined switch operands too. 2023-08-12 02:46:31 +02:00
Charlotte bf84861fc2 proc_clean: only consider fully-defined case operands. 2023-08-12 02:46:31 +02:00
whitequark d51ecde8c2 clean: keep $print cells, since they have unmodelled side effects. 2023-08-11 04:46:52 +02:00