mirror of https://github.com/YosysHQ/yosys.git
proc_clean: only consider fully-defined case operands.
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@ -41,7 +41,7 @@ void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did
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break;
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for (int j = 0; j < int(cs->compare.size()); j++) {
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RTLIL::SigSpec &val = cs->compare[j];
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if (!val.is_fully_const())
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if (!val.is_fully_def())
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continue;
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if (val == sw->signal) {
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cs->compare.clear();
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@ -0,0 +1,22 @@
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read_rtlil <<EOT
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module \m
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wire width 1 \w
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process $p
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switch 3'001
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case 3'--1
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assign \w 3'001
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case 3'-1-
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assign \w 3'010
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case 3'1--
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assign \w 3'100
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end
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end
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end
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EOT
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proc_clean # Bug: removes the cases.
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proc_clean # Removes the now-empty switch and its containing process.
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select -assert-count 1 */p:*
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