mirror of https://github.com/YosysHQ/yosys.git
proc_clean: only consider fully-defined switch operands too.
This commit is contained in:
parent
bf84861fc2
commit
860e3e4056
|
@ -31,7 +31,7 @@ PRIVATE_NAMESPACE_BEGIN
|
|||
|
||||
void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &count, int max_depth)
|
||||
{
|
||||
if (sw->signal.size() > 0 && sw->signal.is_fully_const())
|
||||
if (sw->signal.size() > 0 && sw->signal.is_fully_def())
|
||||
{
|
||||
int found_matching_case_idx = -1;
|
||||
for (int i = 0; i < int(sw->cases.size()) && found_matching_case_idx < 0; i++)
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
read_rtlil <<EOT
|
||||
|
||||
module \m
|
||||
module \a
|
||||
wire width 1 \w
|
||||
process $p
|
||||
switch 3'001
|
||||
|
@ -14,9 +14,24 @@ module \m
|
|||
end
|
||||
end
|
||||
|
||||
module \b
|
||||
wire width 1 \w
|
||||
process $p
|
||||
switch 3'--1
|
||||
case 3'001
|
||||
assign \w 3'001
|
||||
case 3'010
|
||||
assign \w 3'010
|
||||
case 3'100
|
||||
assign \w 3'100
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
EOT
|
||||
|
||||
proc_clean # Bug: removes the cases.
|
||||
proc_clean # Removes the now-empty switch and its containing process.
|
||||
|
||||
select -assert-count 1 */p:*
|
||||
select -assert-count 1 a/p:*
|
||||
select -assert-count 1 b/p:*
|
||||
|
|
Loading…
Reference in New Issue