From 860e3e40563e6d5096ba0b7b1e81d25a70deb58c Mon Sep 17 00:00:00 2001
From: Charlotte <charlotte@lottia.net>
Date: Fri, 11 Aug 2023 16:34:00 +1000
Subject: [PATCH] proc_clean: only consider fully-defined switch operands too.

---
 passes/proc/proc_clean.cc      |  2 +-
 tests/proc/clean_undef_case.ys | 19 +++++++++++++++++--
 2 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc
index 6ce2f8cb0..95cb0e88c 100644
--- a/passes/proc/proc_clean.cc
+++ b/passes/proc/proc_clean.cc
@@ -31,7 +31,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 void proc_clean_switch(RTLIL::SwitchRule *sw, RTLIL::CaseRule *parent, bool &did_something, int &count, int max_depth)
 {
-	if (sw->signal.size() > 0 && sw->signal.is_fully_const())
+	if (sw->signal.size() > 0 && sw->signal.is_fully_def())
 	{
 		int found_matching_case_idx = -1;
 		for (int i = 0; i < int(sw->cases.size()) && found_matching_case_idx < 0; i++)
diff --git a/tests/proc/clean_undef_case.ys b/tests/proc/clean_undef_case.ys
index 3c29c93bc..c874b08c0 100644
--- a/tests/proc/clean_undef_case.ys
+++ b/tests/proc/clean_undef_case.ys
@@ -1,6 +1,6 @@
 read_rtlil <<EOT
 
-module \m
+module \a
   wire width 1 \w
   process $p
     switch 3'001
@@ -14,9 +14,24 @@ module \m
   end
 end
 
+module \b
+  wire width 1 \w
+  process $p
+    switch 3'--1
+      case 3'001
+        assign \w 3'001
+      case 3'010
+        assign \w 3'010
+      case 3'100
+        assign \w 3'100
+    end
+  end
+end
+
 EOT
 
 proc_clean  # Bug: removes the cases.
 proc_clean  # Removes the now-empty switch and its containing process.
 
-select -assert-count 1 */p:*
+select -assert-count 1 a/p:*
+select -assert-count 1 b/p:*