mirror of https://github.com/YosysHQ/yosys.git
dft_tag: Fix size extending $x[n]or and $reduce_{or,bool}/$logic_not
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20024900d9
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@ -405,7 +405,7 @@ struct DftTagWorker {
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auto &sig_y = cell->getPort(ID::Y);
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auto sig_a = cell->getPort(ID::A);
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auto sig_b = cell->getPort(ID::B);
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if (cell->type.in(ID($and), ID($or))) {
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if (cell->type.in(ID($and), ID($or), ID($xor), ID($xnor))) {
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sig_a.extend_u0(GetSize(sig_y), cell->getParam(ID::A_SIGNED).as_bool());
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sig_b.extend_u0(GetSize(sig_y), cell->getParam(ID::B_SIGNED).as_bool());
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}
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@ -669,12 +669,12 @@ struct DftTagWorker {
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auto &sig_y = cell->getPort(ID::Y);
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auto sig_a = cell->getPort(ID::A);
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if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not)))
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sig_a = autoNot(NEW_ID, sig_a);
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auto group_sig_a = tag_group_signal(tag, sig_a);
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auto tag_sig_a = tag_signal(tag, sig_a);
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if (cell->type.in(ID($reduce_or), ID($reduce_bool), ID($logic_not)))
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sig_a = autoNot(NEW_ID, sig_a);
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auto filled = autoOr(NEW_ID, sig_a, group_sig_a);
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auto prop = autoReduceAnd(NEW_ID, filled);
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