multpass.cc -> booth.cc, added author/support contact info

This commit is contained in:
andyfox-rushc 2023-09-11 11:39:13 -07:00
parent 1b5287af59
commit a2c8e47295
2 changed files with 9 additions and 8 deletions

View File

@ -4,7 +4,7 @@ OBJS += passes/techmap/techmap.o
OBJS += passes/techmap/simplemap.o
OBJS += passes/techmap/dfflibmap.o
OBJS += passes/techmap/maccmap.o
OBJS += passes/techmap/multpass.o
OBJS += passes/techmap/booth.o
OBJS += passes/techmap/libparse.o
ifeq ($(ENABLE_ABC),1)
@ -30,9 +30,6 @@ OBJS += passes/techmap/extract_reduce.o
OBJS += passes/techmap/alumacc.o
OBJS += passes/techmap/dffinit.o
OBJS += passes/techmap/pmuxtree.o
OBJS += passes/techmap/bmuxmap.o
OBJS += passes/techmap/demuxmap.o
OBJS += passes/techmap/bwmuxmap.o
OBJS += passes/techmap/muxcover.o
OBJS += passes/techmap/aigmap.o
OBJS += passes/techmap/tribuf.o

View File

@ -1,6 +1,7 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2023 Andy Fox <andy@rushc.com> https://www.linkedin.com/in/awfox/
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
@ -17,8 +18,8 @@
*/
/*
MultPass
--------
Booth Pass
----------
Replace $mul with booth encoded multipliers. Two different
architectures used for signed/unsigned.
@ -31,13 +32,13 @@
http://i.stanford.edu/pub/cstr/reports/csl/tr/94/617/CSL-TR-94-617.pdf
How to use:
Add multpass to your yosys script eg:
Add booth pass to your yosys script eg:
read_verilog smultiply5_rtl.v
opt
wreduce
opt
multpass
booth
alumacc
maccmap
opt
@ -46,6 +47,9 @@
abc -liberty NangateOpenCellLibrary_typical.lib
stat -liberty NangateOpenCellLibrary_typical.lib
write_verilog -norename booth_final.v
or in generic synthesis call with -booth argument:
synth -top my_design -booth
*/
#include "kernel/sigtools.h"