mirror of https://github.com/YosysHQ/yosys.git
sim: Add -noinitstate option and handle non-cosim initstate
This adds the -noinitstate option which is required to simulate counterexamples to induction with yw-cosim. Also add handling for $initstate cells for non-co-simulation.
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20024900d9
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7eaa4bcb46
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@ -111,6 +111,7 @@ struct SimShared
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int step = 0;
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std::vector<TriggeredAssertion> triggered_assertions;
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bool serious_asserts = false;
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bool initstate = true;
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};
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void zinit(State &v)
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@ -1356,6 +1357,8 @@ struct SimWorker : SimShared
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set_inports(clock, State::Sx);
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set_inports(clockn, State::Sx);
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top->set_initstate_outputs(initstate ? State::S1 : State::S0);
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update(false);
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register_output_step(0);
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@ -1372,6 +1375,9 @@ struct SimWorker : SimShared
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update(true);
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register_output_step(10*cycle + 5);
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if (cycle == 0)
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top->set_initstate_outputs(State::S0);
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if (debug)
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log("\n===== %d =====\n", 10*cycle + 10);
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else if (verbose)
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@ -1953,7 +1959,7 @@ struct SimWorker : SimShared
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if (yw.steps.empty()) {
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log_warning("Yosys witness file `%s` contains no time steps\n", yw.filename.c_str());
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} else {
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top->set_initstate_outputs(State::S1);
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top->set_initstate_outputs(initstate ? State::S1 : State::S0);
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set_yw_state(yw, hierarchy, 0);
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set_yw_clocks(yw, hierarchy, true);
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initialize_stable_past();
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@ -2546,6 +2552,9 @@ struct SimPass : public Pass {
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log(" -n <integer>\n");
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log(" number of clock cycles to simulate (default: 20)\n");
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log("\n");
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log(" -noinitstate\n");
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log(" do not activate $initstate cells during the first cycle\n");
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log("\n");
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log(" -a\n");
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log(" use all nets in VCD/FST operations, not just those with public names\n");
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log("\n");
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@ -2646,6 +2655,10 @@ struct SimPass : public Pass {
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worker.cycles_set = true;
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continue;
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}
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if (args[argidx] == "-noinitstate") {
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worker.initstate = false;
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continue;
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}
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if (args[argidx] == "-rstlen" && argidx+1 < args.size()) {
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worker.rstlen = atoi(args[++argidx].c_str());
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continue;
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