mirror of https://github.com/YosysHQ/yosys.git
Revert changes to techmap.cc.
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67f1700486
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1bbc12f389
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@ -156,6 +156,8 @@ struct TechmapWorker
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}
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std::string orig_cell_name;
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pool<string> extra_src_attrs = cell->get_strpool_attribute(ID::src);
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orig_cell_name = cell->name.str();
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for (auto tpl_cell : tpl->cells())
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if (tpl_cell->name.ends_with("_TECHMAP_REPLACE_")) {
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@ -170,7 +172,7 @@ struct TechmapWorker
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apply_prefix(cell->name, m_name);
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RTLIL::Memory *m = module->addMemory(m_name, it.second);
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if (m->attributes.count(ID::src))
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m->attributes[ID::src] = cell->attributes[ID::src];
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m->add_strpool_attribute(ID::src, extra_src_attrs);
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memory_renames[it.first] = m->name;
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design->select(module, m);
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}
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@ -215,7 +217,7 @@ struct TechmapWorker
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if (tpl_w->get_bool_attribute(ID::_techmap_special_))
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w->attributes.clear();
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if (w->attributes.count(ID::src))
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w->attributes[ID::src] = cell->attributes[ID::src];
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w->add_strpool_attribute(ID::src, extra_src_attrs);
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}
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design->select(module, w);
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@ -373,7 +375,7 @@ struct TechmapWorker
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}
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if (c->attributes.count(ID::src))
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c->attributes[ID::src] = cell->attributes[ID::src];
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c->add_strpool_attribute(ID::src, extra_src_attrs);
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if (techmap_replace_cell) {
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for (auto attr : cell->attributes)
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