mirror of https://github.com/YosysHQ/yosys.git
ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech
This commit is contained in:
parent
4a475fa7a2
commit
a8809989c4
|
@ -39,7 +39,7 @@ struct OptLutInsPass : public Pass {
|
|||
log("\n");
|
||||
log(" -tech <technology>\n");
|
||||
log(" Instead of generic $lut cells, operate on LUT cells specific\n");
|
||||
log(" to the given technology. Valid values are: xilinx, ecp5, gowin.\n");
|
||||
log(" to the given technology. Valid values are: xilinx, lattice, gowin.\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
|
@ -58,7 +58,7 @@ struct OptLutInsPass : public Pass {
|
|||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
if (techname != "" && techname != "xilinx" && techname != "ecp5" && techname != "gowin")
|
||||
if (techname != "" && techname != "xilinx" && techname != "lattice" && techname != "ecp5" && techname != "gowin")
|
||||
log_cmd_error("Unsupported technology: '%s'\n", techname.c_str());
|
||||
|
||||
for (auto module : design->selected_modules())
|
||||
|
@ -130,7 +130,7 @@ struct OptLutInsPass : public Pass {
|
|||
output = cell->getPort(ID::O);
|
||||
else
|
||||
output = cell->getPort(ID::F);
|
||||
} else if (techname == "ecp5") {
|
||||
} else if (techname == "lattice" || techname == "ecp5") {
|
||||
if (cell->type == ID(LUT4)) {
|
||||
inputs = {
|
||||
cell->getPort(ID::A),
|
||||
|
@ -181,7 +181,7 @@ struct OptLutInsPass : public Pass {
|
|||
if (!doit)
|
||||
continue;
|
||||
log(" Optimizing lut %s (%d -> %d)\n", log_id(cell), GetSize(inputs), GetSize(new_inputs));
|
||||
if (techname == "ecp5") {
|
||||
if (techname == "lattice" || techname == "ecp5") {
|
||||
// Pad the LUT to 4 inputs, adding consts from the front.
|
||||
int extra = 4 - GetSize(new_inputs);
|
||||
log_assert(extra >= 0);
|
||||
|
@ -215,9 +215,9 @@ struct OptLutInsPass : public Pass {
|
|||
}
|
||||
new_lut[i] = lut[lidx];
|
||||
}
|
||||
// For ecp5, and gowin do not replace with a const driver — the nextpnr
|
||||
// For lattice, and gowin do not replace with a const driver — the nextpnr
|
||||
// packer requires a complete set of LUTs for wide LUT muxes.
|
||||
if (new_inputs.empty() && techname != "ecp5" && techname != "gowin") {
|
||||
if (new_inputs.empty() && techname != "lattice" && techname != "ecp5" && techname != "gowin") {
|
||||
// const driver.
|
||||
remove_cells.push_back(cell);
|
||||
module->connect(output, new_lut[0]);
|
||||
|
@ -226,7 +226,7 @@ struct OptLutInsPass : public Pass {
|
|||
cell->setParam(ID::LUT, new_lut);
|
||||
cell->setParam(ID::WIDTH, GetSize(new_inputs));
|
||||
cell->setPort(ID::A, new_inputs);
|
||||
} else if (techname == "ecp5") {
|
||||
} else if (techname == "lattice" || techname == "ecp5") {
|
||||
log_assert(GetSize(new_inputs) == 4);
|
||||
cell->setParam(ID::INIT, new_lut);
|
||||
cell->setPort(ID::A, new_inputs[0]);
|
||||
|
|
|
@ -1,5 +1,5 @@
|
|||
|
||||
OBJS += techlibs/ecp5/synth_ecp5.o techlibs/ecp5/ecp5_gsr.o
|
||||
OBJS += techlibs/ecp5/synth_ecp5.o
|
||||
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_ff.vh))
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/cells_io.vh))
|
||||
|
|
|
@ -359,7 +359,7 @@ struct SynthEcp5Pass : public ScriptPass
|
|||
run("techmap -D NO_LUT -map +/ecp5/cells_map.v");
|
||||
run("opt_expr -undriven -mux_undef");
|
||||
run("simplemap");
|
||||
run("ecp5_gsr");
|
||||
run("lattice_gsr");
|
||||
run("attrmvcp -copy -attr syn_useioff");
|
||||
run("opt_clean");
|
||||
}
|
||||
|
@ -404,7 +404,7 @@ struct SynthEcp5Pass : public ScriptPass
|
|||
run("techmap -map +/ecp5/cells_map.v", "(skip if -vpr)");
|
||||
else if (!vpr)
|
||||
run("techmap -map +/ecp5/cells_map.v");
|
||||
run("opt_lut_ins -tech ecp5");
|
||||
run("opt_lut_ins -tech lattice");
|
||||
run("clean");
|
||||
}
|
||||
|
||||
|
|
|
@ -0,0 +1 @@
|
|||
OBJS += techlibs/lattice/lattice_gsr.o
|
|
@ -24,13 +24,13 @@
|
|||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
struct Ecp5GsrPass : public Pass {
|
||||
Ecp5GsrPass() : Pass("ecp5_gsr", "ECP5: handle GSR") { }
|
||||
struct LatticeGsrPass : public Pass {
|
||||
LatticeGsrPass() : Pass("lattice_gsr", "Lattice: handle GSR") { }
|
||||
void help() override
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" ecp5_gsr [options] [selection]\n");
|
||||
log(" lattice_gsr [options] [selection]\n");
|
||||
log("\n");
|
||||
log("Trim active low async resets connected to GSR and resolve GSR parameter,\n");
|
||||
log("if a GSR or SGSR primitive is used in the design.\n");
|
||||
|
@ -42,7 +42,7 @@ struct Ecp5GsrPass : public Pass {
|
|||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) override
|
||||
{
|
||||
log_header(design, "Executing ECP5_GSR pass (implement FF init values).\n");
|
||||
log_header(design, "Executing LATTICE_GSR pass (implement FF init values).\n");
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
|
@ -130,6 +130,6 @@ struct Ecp5GsrPass : public Pass {
|
|||
|
||||
}
|
||||
}
|
||||
} Ecp5GsrPass;
|
||||
} LatticeGsrPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
|
@ -239,7 +239,7 @@ struct SynthMachXO2Pass : public ScriptPass
|
|||
run("techmap -D NO_LUT -map +/machxo2/cells_map.v");
|
||||
run("opt_expr -undriven -mux_undef");
|
||||
run("simplemap");
|
||||
run("ecp5_gsr");
|
||||
run("lattice_gsr");
|
||||
run("attrmvcp -copy -attr syn_useioff");
|
||||
run("opt_clean");
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue