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2317 Commits

Author SHA1 Message Date
Ahmed Irfan e82e4f7df4 Update README 
pmux cell is implemented
 2015-04-03 16:45:14 +02:00
Ahmed Irfan ea2e0297d5 separated memory next from write cell 2015-04-03 16:41:50 +02:00
Ahmed Irfan bdf6b2b19a Merge branch 'master' of https://github.com/cliffordwolf/yosys 2015-04-03 16:38:07 +02:00
Ahmed Irfan 8acdd90bc9 Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys into btor 2015-04-03 16:34:05 +02:00
Ahmed Irfan 7ad179151b appnote for verilog to btor 2015-04-03 16:20:29 +02:00
Clifford Wolf 4b44907619 documentation improvements 2015-03-29 20:22:08 +02:00
Clifford Wolf a923a63a89 Ignore celldefine directive in verilog front-end 2015-03-25 19:46:12 +01:00
Clifford Wolf e468d4cc60 Fixes in cmos_cells.v 2015-03-25 09:00:41 +01:00
Clifford Wolf 68bbb15214 Fixed detection of absolute paths in ABC for win32 2015-03-22 11:03:56 +01:00
Clifford Wolf 611cd010ae Added blif reference to appnote 010 2015-03-22 09:49:46 +01:00
Clifford Wolf 6f8547bfc6 Merge branch 'master' of github.com:cliffordwolf/yosys 2015-03-20 09:10:16 +01:00
Clifford Wolf 604c097f98 fix for python 2.6.6 2015-03-20 09:10:02 +01:00
Clifford Wolf 8b1e0bdd9e Fixed handling of quotes in liberty parser 2015-03-18 16:03:19 +01:00
Clifford Wolf aed4d763cf Added hierarchy -auto-top 2015-03-18 08:33:40 +01:00
Clifford Wolf 67e6dcd34a Added Verilog backend $dffsr support 2015-03-18 08:01:37 +01:00
Clifford Wolf 6c8fdb1829 Documentation for JSON format, added attributes 2015-03-06 10:21:21 +01:00
Clifford Wolf 42d5d94a5d Added very first version of "synth_ice40" 2015-03-05 20:37:55 +01:00
Clifford Wolf ed15400fc6 Fixed bug in "hierarchy" for parametric designs 2015-03-04 15:52:34 +01:00
Clifford Wolf adc12ce46e Json bugfix 2015-03-03 09:41:41 +01:00
Clifford Wolf 4fc63f27a1 Json backend improvements 2015-03-03 09:28:44 +01:00
Clifford Wolf 795a6e1d04 Added write_blif -attr 2015-03-02 23:47:45 +01:00
Clifford Wolf 8b488983d0 Added JSON backend 2015-03-02 23:30:58 +01:00
Clifford Wolf 422794c584 Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker() 2015-03-01 11:20:22 +01:00
Clifford Wolf 5d4f513c3b Added $assume support to write_smt2 2015-02-26 19:02:55 +01:00
Clifford Wolf 1f1deda888 Added non-std verilog assume() statement 2015-02-26 18:47:39 +01:00
Clifford Wolf b005eedf36 Added $assume cell type 2015-02-26 18:04:10 +01:00
Clifford Wolf 27a918eadf Merge branch 'master' of github.com:cliffordwolf/yosys 2015-02-25 23:01:54 +01:00
Clifford Wolf 331f8b8d0b Bugfix in iopadmap 2015-02-25 23:01:42 +01:00
Clifford Wolf 3fe18c26cd Added "keep_hierarchy" attribute 2015-02-25 12:46:00 +01:00
Clifford Wolf 9ae21263f0 Some cleanups in "clean" 2015-02-24 22:31:30 +01:00
Clifford Wolf 81fa4e81a6 Fixed compilation problems with gcc 4.6.3; use enum instead of const ints. 
(original patch by Andrew Becker <andrew.becker@epfl.ch>)
 2015-02-24 11:01:00 +01:00
Clifford Wolf ff3f2448b1 Minor "write_smt2" help msg change 2015-02-22 16:30:02 +01:00
Clifford Wolf c4f383e452 Fixed "check -assert" 2015-02-22 16:29:44 +01:00
Clifford Wolf 4b89dd983c Added "<mod>_a" and "<mod>_i" to write_smt2 output 2015-02-22 16:19:10 +01:00
Clifford Wolf d361d313e1 Added "check -assert" doc 2015-02-22 13:02:48 +01:00
Clifford Wolf e8307cefd9 Added "check -assert" 2015-02-22 13:00:41 +01:00
Clifford Wolf 39d25b212c Fixed "sat -initsteps" off-by-one bug 2015-02-22 12:42:05 +01:00
Clifford Wolf fae0e75ace Added "sat -stepsize" and "sat -tempinduct-step" 2015-02-21 22:52:49 +01:00
Clifford Wolf b19c926af8 sat docu change 2015-02-21 22:03:54 +01:00
Clifford Wolf 9237fb924e When "sat -tempinduct-baseonly -maxsteps N" reaches maxsteps it is a good thing. 2015-02-21 20:05:16 +01:00
Clifford Wolf 1688b9b464 Added "sat -tempinduct-baseonly -tempinduct-inductonly" 2015-02-21 17:53:22 +01:00
Clifford Wolf dcbd00c101 Fixed basecase init for "sat -tempinduct" 2015-02-21 17:43:49 +01:00
Clifford Wolf 49dd9c713f Fixed "flatten" for non-pre-derived modules 2015-02-21 15:01:13 +01:00
Clifford Wolf 1f6737f08f Hotfix for yosysjs/demo03.html 2015-02-21 14:31:02 +01:00
Clifford Wolf 1fe15a5973 YosysJS: Wait for Viz to load 2015-02-21 14:25:34 +01:00
Clifford Wolf 4e6ca7760f Replaced ezDefaultSAT with ezSatPtr 2015-02-21 12:15:41 +01:00
Clifford Wolf f778a4081c Catch constants assigned to cell outputs in "flatten" 2015-02-21 11:21:28 +01:00
Clifford Wolf d5ce9a32ef Added deep recursion warning to AST simplify 2015-02-20 10:33:20 +01:00
Clifford Wolf dc1a0f06fc Parser support for complex delay expressions 2015-02-20 10:21:36 +01:00
Clifford Wolf 78b991d760 YosysJS firefox fixes 2015-02-19 13:55:36 +01:00