Commit Graph

318 Commits

Author SHA1 Message Date
Charlotte 4e94f62116 simlib: blackbox `$print` cell
It's possible to `generate` the appropriate always blocks per the
triggers, but unlikely to be worth parsing the RTLIL \FORMAT parameter.
2023-08-11 04:46:52 +02:00
Jannis Harder 7203ba7bc1 Add bitwise `$bweqx` and `$bwmux` cells
The new bitwise case equality (`$bweqx`) and bitwise mux (`$bwmux`)
cells enable compact encoding and decoding of 3-valued logic signals
using multiple 2-valued signals.
2022-11-30 18:24:35 +01:00
Jannis Harder 99163fb822 simlib: Use optional SIMLIB_GLOBAL_CLOCK to define a global clock signal 2022-11-30 18:24:35 +01:00
Jannis Harder 605d127517 simlib: Silence iverilog warning for `$lut`
iverilog complains about implicitly truncating LUT when connecting it to
the `$bmux` A input. This explicitly truncates it to avoid that warning
without changing the behaviour otherwise.
2022-11-30 18:24:35 +01:00
Jannis Harder 39ac113402 simlib: Fix wide $bmux and avoid iverilog warnings 2022-11-30 18:24:35 +01:00
Jannis Harder b982ab4f59 satgen, simlib: Consistent x-propagation for `$pmux` cells
This updates satgen and simlib to use a `$pmux` model where the output
is fully X when the S input is not all zero or one-hot with no x bits.
2022-11-30 18:24:35 +01:00
Jannis Harder aa7e7df19f simlib: Simplify recently changed $mux model
The use of a procedural continuous assignment introduced in #3526 was
unintended and is completely unnecessary for the actual change of that
PR.
2022-10-28 19:48:00 +02:00
Jannis Harder 408fc60c95
Merge pull request #3526 from jix/mux-simlib-eval
Consistent $mux undef handling
2022-10-24 16:25:33 +02:00
Jannis Harder c77b7343d0 Consistent $mux undef handling
* Change simlib's $mux cell to use the ternary operator as $_MUX_
  already does
* Stop opt_expr -keepdc from changing S=x to S=0
* Change const eval of $mux and $pmux to match the updated simlib
  (fixes sim)
* The sat behavior of $mux already matches the updated simlib

The verilog frontend uses $mux for the ternary operators and this
changes all interpreations of the $mux cell (that I found) to match the
verilog simulation behavior for the ternary operator. For 'if' and
'case' expressions the frontend may also use $mux but uses $eqx if the
verilog simulation behavior is requested with the '-ifx' option.

For $pmux there is a remaining mismatch between the sat behavior and the
simlib behavior. Resolving this requires more discussion, as the $pmux
cell does not directly correspond to a specific verilog construct.
2022-10-24 12:03:01 +02:00
Jannis Harder 0f96ae5990 Add smtmap.v describing the smt2 backend's behavior for undef bits
Some builtin cells have an undefined (x) output even when all inputs are
defined. This is not natively supported by the formal backends which
will produce a fully defined value instead. This can lead to issues when
combining different backends in a formal flow. To work around these,
this adds a file containing verilog implementation of cells matching the
fully defined behavior implemented by the smt2 backend.
2022-10-20 15:48:18 +02:00
Jannis Harder c0063288d6 Add the $anyinit cell and the formalff pass
These can be used to protect undefined flip-flop initialization values
from optimizations that are not sound for formal verification and can
help mapping all solver-provided values in witness traces for flows that
use different backends simultaneously.
2022-08-16 13:37:30 +02:00
Marcelina Kościelnicka 71dfbf33b2 Add -no-rw-check option to memory_dff + memory + synth_{ice40,ecp5,gowin}. 2022-06-02 23:16:12 +02:00
Marcelina Kościelnicka 93508d58da Add $bmux and $demux cells. 2022-01-28 23:34:41 +01:00
Marcelina Kościelnicka e7d89e653c Hook up $aldff support in various passes. 2021-10-02 21:01:21 +02:00
Marcelina Kościelnicka ec2b5548fe Add $aldff and $aldffe: flip-flops with async load. 2021-10-02 18:12:52 +02:00
Marcelina Kościelnicka fd79217763 Add v2 memory cells. 2021-08-11 13:34:10 +02:00
Marcelina Kościelnicka 19720b970d memory: Introduce $meminit_v2 cell, with EN input. 2021-07-28 23:18:38 +02:00
Claire Xenia Wolf 92e705cb51 Fix files with CRLF line endings 2021-06-09 12:16:33 +02:00
Claire Xenia Wolf 72787f52fc Fixing old e-mail addresses and deadnames
s/((Claire|Xen|Xenia|Clifford)\s+)+(Wolf|Xen)\s+<(claire|clifford)@(symbioticeda.com|clifford.at|yosyshq.com)>/Claire Xenia Wolf <claire@yosyshq.com>/gi;
s/((Nina|Nak|N\.)\s+)+Engelhardt\s+<nak@(symbioticeda.com|yosyshq.com)>/N. Engelhardt <nak@yosyshq.com>/gi;
s/((David)\s+)+Shah\s+<(dave|david)@(symbioticeda.com|yosyshq.com|ds0.me)>/David Shah <dave@ds0.me>/gi;
s/((Miodrag)\s+)+Milanovic\s+<(miodrag|micko)@(symbioticeda.com|yosyshq.com)>/Miodrag Milanovic <micko@yosyshq.com>/gi;
s,https?://www.clifford.at/yosys/,http://yosyshq.net/yosys/,g;
2021-06-08 00:39:36 +02:00
Eddie Hung 55dc5a4e4f
abc9: fix SCC issues (#2694)
* xilinx: add SCC test for DSP48E1

* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1

Have a test that checks it works through ABC9 when enabled

* abc9 to break SCCs using $__ABC9_SCC_BREAKER module

* Add test

* abc9_ops: remove refs to (* abc9_keep *) on wires

* abc9_ops: do not bypass cells in an SCC

* Add myself to CODEOWNERS for abc9*

* Fix compile

* abc9_ops: run -prep_hier before scc

* Fix tests

* Remove bug reference pending fix

* abc9: fix for -prep_hier -dff

* xaiger: restore PI handling

* abc9_ops: -prep_xaiger sigmap

* abc9_ops: -mark_scc -> -break_scc

* abc9: eliminate hard-coded abc9.box from tests

Also tidy up

* Address review
2021-03-29 22:01:57 -07:00
Marcelina Kościelnicka a3528649c8 memory_dff: Remove now-useless write port handling. 2021-03-08 20:16:29 +01:00
Marcelina Kościelnicka cde73428b0 Fix syntax error in adff2dff.v
Fixes #2600.
2021-02-24 01:07:34 +01:00
Zachary Snow fe74b0cd95 verilog: significant block scoping improvements
This change set contains a number of bug fixes and improvements related to
scoping and resolution in generate and procedural blocks. While many of the
frontend changes are interdependent, it may be possible bring the techmap
changes in under a separate PR.

Declarations within unnamed generate blocks previously encountered issues
because the data declarations were left un-prefixed, breaking proper scoping.
The LRM outlines behavior for generating names for unnamed generate blocks. The
original goal was to add this implicit labelling, but doing so exposed a number
of issues downstream. Additional testing highlighted other closely related scope
resolution issues, which have been fixed. This change also adds support for
block item declarations within unnamed blocks in SystemVerilog mode.

1. Unlabled generate blocks are now implicitly named according to the LRM in
   `label_genblks`, which is invoked at the beginning of module elaboration
2. The Verilog parser no longer wraps explicitly named generate blocks in a
   synthetic unnamed generate block to avoid creating extra hierarchy levels
   where they should not exist
3. The techmap phase now allows special control identifiers to be used outside
   of the topmost scope, which is necessary because such wires and cells often
   appear in unlabeled generate blocks, which now prefix the declarations within
4. Some techlibs required modifications because they relied on the previous
   invalid scope resolution behavior
5. `expand_genblock` has been simplified, now only expanding the outermost
   scope, completely deferring the inspection and elaboration of nested scopes;
   names are now resolved by looking in the innermost scope and stepping outward
6. Loop variables now always become localparams during unrolling, allowing them
   to be resolved and shadowed like any other identifier
7. Identifiers in synthetic function call scopes are now prefixed and resolved
   in largely the same manner as other blocks
     before: `$func$\func_01$tests/simple/scopes.blk.v:60$5$\blk\x`
      after: `\func_01$func$tests/simple/scopes.v:60$5.blk.x`
8. Support identifiers referencing a local generate scope nested more
   than 1 level deep, i.e. `B.C.x` while within generate scope `A`, or using a
   prefix of a current or parent scope, i.e. `B.C.D.x` while in `A.B`, `A.B.C`,
   or `A.B.C.D`
9. Variables can now be declared within unnamed blocks in SystemVerilog mode

Addresses the following issues: 656, 2423, 2493
2021-01-31 09:42:09 -05:00
Tom Verbeure 87637e8359 Fix some trivial typos. 2021-01-03 23:52:59 -08:00
clairexen d9dd8bc748
Merge pull request #2347 from YosysHQ/mwk/techmap-shift-fixes
techmap/shift_shiftx: Remove the "shiftx2mux" special path.
2020-08-20 16:25:56 +02:00
clairexen 1cdb533fa5
Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-pattern
techmap: Add support for [] wildcards in techmap_celltype.
2020-08-20 16:18:40 +02:00
Marcelina Kościelnicka 50d532f01c techmap/shift_shiftx: Remove the "shiftx2mux" special path.
Our techmap rules for $shift and $shiftx cells contained a special path
that aimed to decompose the shift LSB-first instead of MSB-first in
select cases that come up in pmux lowering.  This path was needlessly
overcomplicated and contained bugs.

Instead of doing that, just switch over the main path to iterate
LSB-first (except for the specially-handled MSB for signed shifts
and overflow handling).  This also makes the code consistent with
shl/shr/sshl/sshr cells, which are already decomposed LSB-first.

Fixes #2346.
2020-08-20 12:44:09 +02:00
Xiretza 928fd40c2e Respect \A_SIGNED for $shift
This reflects the behaviour of $shr/$shl, which sign-extend their A
operands to the size of their output, then do a logical shift (shift in
0-bits).
2020-08-18 19:36:24 +02:00
Marcelina Kościelnicka 9a4f420b4b Replace opt_rmdff with opt_dff. 2020-08-07 13:21:03 +02:00
Marcelina Kościelnicka 522788f016 techmap: Add support for [] wildcards in techmap_celltype.
Fixes #1826.
2020-08-02 22:46:48 +02:00
Marcelina Kościelnicka 817ae04ee0 simcells: Fix reset polarity for $_DLATCH_???_ cells. 2020-06-30 15:32:06 +02:00
Marcelina Kościelnicka 832acc8648 Add new FF types to simplemap. 2020-06-23 15:40:02 +02:00
Marcelina Kościelnicka b0bee396a8 Add new builtin FF types
The new types include:

- FFs with async reset and enable (`$adffe`, `$_DFFE_[NP][NP][01][NP]_`)
- FFs with sync reset (`$sdff`, `$_SDFF_[NP][NP][01]_`)
- FFs with sync reset and enable, reset priority (`$sdffs`, `$_SDFFE_[NP][NP][01][NP]_`)
- FFs with sync reset and enable, enable priority (`$sdffce`, `$_SDFFCE_[NP][NP][01][NP]_`)
- FFs with async reset, set, and enable (`$dffsre`, `$_DFFSRE_[NP][NP][NP][NP]_`)
- latches with reset or set (`$adlatch`, `$_DLATCH_[NP][NP][01]_`)

The new FF types are not actually used anywhere yet (this is left
for future commits).
2020-06-23 15:40:02 +02:00
whitequark 7191dd16f9 Use C++11 final/override keywords. 2020-06-18 23:34:52 +00:00
Claire Wolf 3c7122c378 Do not optimize away FFs in "prep" and Verific fron-end
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
2020-06-09 15:54:14 +02:00
Eddie Hung 69850204c4
Merge pull request #2077 from YosysHQ/eddie/abc9_dff_improve
abc9: -dff improvements
2020-06-04 08:15:25 -07:00
Eddie Hung d3b53bc495 abc9_ops: -reintegrate use SigMap to remove (* init *) from $_DFF_[NP]_ 2020-05-29 17:17:40 -07:00
Xiretza edd8ff2c07
Add flooring division operator
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $divfloor cell provides this flooring division.

This commit also fixes the handling of $div in opt_expr, which was
previously optimized as if it was $divfloor.
2020-05-28 22:59:04 +02:00
Xiretza 17163cf43a
Add flooring modulo operator
The $div and $mod cells use truncating division semantics (rounding
towards 0), as defined by e.g. Verilog. Another rounding mode, flooring
(rounding towards negative infinity), can be used in e.g. VHDL. The
new $modfloor cell provides this flooring modulo (also known as "remainder"
in several languages, but this name is ambiguous).

This commit also fixes the handling of $mod in opt_expr, which was
previously optimized as if it was $modfloor.
2020-05-28 22:59:03 +02:00
Marcelina Kościelnicka aee439360b Add force_downto and force_upto wire attributes.
Fixes #2058.
2020-05-19 01:42:40 +02:00
Eddie Hung 67fc0c3698 abc9: use (* abc9_keep *) instead of (* abc9_scc *); apply to $_DFF_?_
instead of moving them to $__ prefix
2020-05-14 16:44:35 -07:00
Eddie Hung 13f9d65b6f abc9: preserve $_DFF_?_.Q's (* init *); rely on clean to remove it 2020-05-14 10:33:57 -07:00
Eddie Hung 97a0a04314 abc9_ops/xaiger: further reducing Module::derive() calls by ...
replacing _all_ (* abc9_box *) instantiations with their derived types
2020-05-14 10:33:57 -07:00
Eddie Hung e79127fceb Cleanup; reduce Module::derive() calls 2020-05-14 10:33:57 -07:00
Eddie Hung 57c478c537 abc9: only do +/abc9_map if `DFF 2020-05-14 10:33:57 -07:00
Eddie Hung 722540dbf9 abc9: not enough to techmap_fail on (* init=1 *), hide them using $__ 2020-05-14 10:33:56 -07:00
Eddie Hung 48052ad813 abc9: add flop boxes to basic $_DFF_P_ and $_DFF_N_ too 2020-05-14 10:33:56 -07:00
Eddie Hung 95763c8d18 abc9_ops: add 'dff' label for auto handling of (* abc9_flop *) boxes 2020-05-14 10:33:56 -07:00
Eddie Hung 004999218f techlibs/common: more robustness when *_WIDTH = 0 2020-05-05 08:01:27 -07:00
Marcelina Kościelnicka 53ba3cf718 Fix the truth table for $_SR_* cells.
This brings the documented behavior for these cells in line with
$_DFFSR_* and $_DLATCHSR_*, which is that R has priority over S.
The models were already reflecting that behavior.

Also get rid of sim-synth mismatch in the models while we're at it.
2020-04-15 17:17:48 +02:00