mirror of https://github.com/YosysHQ/yosys.git
simlib: Silence iverilog warning for `$lut`
iverilog complains about implicitly truncating LUT when connecting it to the `$bmux` A input. This explicitly truncates it to avoid that warning without changing the behaviour otherwise.
This commit is contained in:
parent
39ac113402
commit
605d127517
|
@ -1377,7 +1377,7 @@ parameter LUT = 0;
|
|||
input [WIDTH-1:0] A;
|
||||
output Y;
|
||||
|
||||
\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT), .S(A), .Y(Y));
|
||||
\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT[(1<<WIDTH)-1:0]), .S(A), .Y(Y));
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
Loading…
Reference in New Issue