From 605d127517163f3d1113a6dbf19abcd55eb63dbb Mon Sep 17 00:00:00 2001
From: Jannis Harder <me@jix.one>
Date: Thu, 10 Nov 2022 16:31:45 +0100
Subject: [PATCH] simlib: Silence iverilog warning for `$lut`

iverilog complains about implicitly truncating LUT when connecting it to
the `$bmux` A input. This explicitly truncates it to avoid that warning
without changing the behaviour otherwise.
---
 techlibs/common/simlib.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 498cc27c2..aca4d21a9 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1377,7 +1377,7 @@ parameter LUT = 0;
 input [WIDTH-1:0] A;
 output Y;
 
-\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT), .S(A), .Y(Y));
+\$bmux #(.WIDTH(1), .S_WIDTH(WIDTH)) mux(.A(LUT[(1<<WIDTH)-1:0]), .S(A), .Y(Y));
 
 endmodule