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@ -11,7 +11,7 @@ module adff2dff (CLK, ARST, D, Q);
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(* force_downto *)
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output reg [WIDTH-1:0] Q;
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(* force_downto *)
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wire reg [WIDTH-1:0] NEXT_Q;
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reg [WIDTH-1:0] NEXT_Q;
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wire [1023:0] _TECHMAP_DO_ = "proc;;";
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