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2992 Commits

Author SHA1 Message Date
Clifford Wolf 7a67add95d Fixed parsing of empty positional cell ports 2016-07-25 12:48:03 +02:00
Clifford Wolf b1c432af56 Improvements in CellEdgesDatabase 2016-07-24 17:21:53 +02:00
Clifford Wolf f162b858f2 Added CellEdgesDatabase API 2016-07-24 13:59:57 +02:00
Clifford Wolf 54966679df Moved SatHelper::setup_init() code to SatHelper::setup() 2016-07-24 12:18:39 +02:00
Clifford Wolf 34e833103b Added $initstate support to "sat" command 2016-07-23 17:01:03 +02:00
Clifford Wolf 9aae1d1e8f No tristate warning message for "read_verilog -lib" 2016-07-23 11:56:53 +02:00
Clifford Wolf 89deb412c6 Added satgen initstate support 2016-07-22 10:28:45 +02:00
Clifford Wolf 7fef5ff104 Using $initstate in "initial assume" and "initial assert" 2016-07-21 14:37:28 +02:00
Clifford Wolf 5c166e76e5 Added $initstate cell type and vlog function 2016-07-21 14:23:22 +02:00
Clifford Wolf d7763634b6 After reading the SV spec, using non-standard predict() instead of expect() 2016-07-21 13:34:33 +02:00
Clifford Wolf 721f1f5ecf Added basic support for $expect cells 2016-07-13 16:56:17 +02:00
Clifford Wolf b3155af5f6 Added examples/smtbmc 2016-07-13 09:49:05 +02:00
Clifford Wolf 2afc72cae3 Merge pull request #191 from whitequark/json-module-attributes 
write_json: also write module attributes
 2016-07-13 09:39:27 +02:00
Clifford Wolf 9e5c9471e3 Merge pull request #193 from azonenberg/master 
Removed splitnets in synth_greenpak4, added GP_DAC, refactored GP_BANDGAP
 2016-07-13 09:24:31 +02:00
Andrew Zonenberg 32bea97b75 Merge https://github.com/cliffordwolf/yosys 2016-07-12 16:12:37 -07:00
Clifford Wolf e92998a79c Minor bugfix in FSM reset state detection 2016-07-12 09:46:15 +02:00
whitequark 546233f0e1 write_json: also write module attributes. 2016-07-12 06:32:04 +00:00
Andrew Zonenberg 52a738a544 Added GP_DAC cell 2016-07-11 22:45:55 -07:00
Andrew Zonenberg baae472b83 Removed VOUT port of GP_BANDGAP 2016-07-11 22:45:42 -07:00
Andrew Zonenberg 8619d33114 Removed splitnets in prep for new gp4par parser 2016-07-11 22:42:25 -07:00
Clifford Wolf c71785d65e Yosys-smtbmc: Support for hierarchical VCD dumping 2016-07-11 12:49:33 +02:00
Clifford Wolf 0153ad85d9 Moved smt2 yosys info parsing from smtbmc.py to smtio.py 2016-07-11 11:49:05 +02:00
Clifford Wolf cdb58f68ab Added "prep -auto-top" and "synth -auto-top" 2016-07-11 11:40:55 +02:00
Clifford Wolf a72fb85dc2 Merge branch 'master' of github.com:cliffordwolf/yosys 2016-07-10 18:17:09 +02:00
Clifford Wolf 307e31a95e Merge pull request #189 from whitequark/master 
greenpak4: add GP_COUNT{8,14}_ADV cells
 2016-07-10 18:12:00 +02:00
Clifford Wolf 771c5fe000 Support for hierarchical designs in smt2 back-end 2016-07-10 18:11:25 +02:00
whitequark c0645839fe greenpak4: add GP_COUNT{8,14}_ADV cells. 2016-07-10 15:46:46 +00:00
Clifford Wolf b5a9fba0db Further improved fsm_detect output, attempt to detect self-resetting circuits 2016-07-09 14:02:49 +02:00
Clifford Wolf d63ffabacb Added printing of some warning messages to fsm_detect 2016-07-09 13:23:06 +02:00
Clifford Wolf d3f0d72427 Added warning about adding fsm_encoding attributes to wires to manual 2016-07-08 18:31:31 +02:00
Clifford Wolf 21659847a7 Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations 2016-07-08 14:41:36 +02:00
Clifford Wolf 9a101dc1f7 Fixed mem assignment in left-hand-side concatenation 2016-07-08 14:31:06 +02:00
Clifford Wolf b782076698 Merge branch 'eddiehung-vtr' 2016-07-08 11:56:53 +02:00
Clifford Wolf 27b5347a87 Restored blif "-true - .." behavior, use "-true + .." for eddiehung-vtr behavior 2016-07-08 11:51:04 +02:00
Clifford Wolf 72149aba2e In BLIF, a .names without entries already always outputs 0 2016-07-08 11:41:26 +02:00
Clifford Wolf 6bda612925 Undo eddiehung-vtr Makefile changes 2016-07-08 11:35:15 +02:00
Clifford Wolf f6b7cf23d6 Merge branch 'yosys-0.5-vtr' of https://github.com/eddiehung/yosys into eddiehung-vtr 2016-07-08 11:32:36 +02:00
Clifford Wolf e420412043 Fixed autotest.sh handling of `timescale 2016-07-02 13:32:20 +02:00
Clifford Wolf 080f95f933 Merge branch 'assert-limit' 2016-07-01 12:24:31 +02:00
Clifford Wolf 6ed6b3cb6d Replaced "select -assert-limit" with -assert-max and -assert-min 2016-07-01 12:24:13 +02:00
eshellko 9a742f4069 Added 'assert-limit' option for 'select' command 
For resource limited designs such as FPGA it can be useful to specify limit of specific resources available on board. So user can check if he should change RTL as early as mapping done.
 2016-07-01 10:24:22 +04:00
Clifford Wolf df5ebfa0a0 Improved ice40_ffinit error reporting 2016-06-30 09:58:13 +02:00
Clifford Wolf 7cddab0788 Merge pull request #181 from rubund/input_logic_allowed 
Allow defining input ports as "input logic" in SystemVerilog
 2016-06-21 08:44:20 +02:00
Ruben Undheim 545bcb37e8 Allow defining input ports as "input logic" in SystemVerilog 2016-06-20 20:16:37 +02:00
Clifford Wolf 541083cf32 Bugfix in "abc -script" handling 2016-06-19 22:19:19 +02:00
Clifford Wolf 9bca8ccd40 Merge branch 'sv_packages' of https://github.com/rubund/yosys 2016-06-19 15:48:40 +02:00
Clifford Wolf ca91bccb6b Added "deminout" 2016-06-19 13:08:16 +02:00
Ruben Undheim a8200a773f A few modifications after pull request comments 
- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
 2016-06-18 14:23:38 +02:00
Clifford Wolf 9e28290b0f Added "read_blif -sop" 2016-06-18 12:33:13 +02:00
Clifford Wolf 5ffad4e073 Added $sop support to BLIF back-end 2016-06-18 12:28:49 +02:00