mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #193 from azonenberg/master
Removed splitnets in synth_greenpak4, added GP_DAC, refactored GP_BANDGAP
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commit
9e5c9471e3
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@ -36,7 +36,7 @@ module GP_ACMP(input wire PWREN, input wire VIN, input wire VREF, output reg OUT
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endmodule
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module GP_BANDGAP(output reg OK, output reg VOUT);
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module GP_BANDGAP(output reg OK);
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parameter AUTO_PWRDN = 1;
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parameter CHOPPER_EN = 1;
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parameter OUT_DELAY = 100;
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@ -120,6 +120,14 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
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endmodule
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module GP_DAC(input[7:0] DIN, input wire VREF, output reg VOUT);
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initial VOUT = 0;
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//analog hard IP is not supported for simulation
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endmodule
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module GP_DELAY(input IN, output reg OUT);
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parameter DELAY_STEPS = 1;
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@ -195,7 +195,6 @@ struct SynthGreenPAK4Pass : public ScriptPass
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if (check_label("json"))
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{
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run("splitnets;;", "(temporary workaround for gp4par parser limitation)");
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if (!json_file.empty() || help_mode)
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run(stringf("write_json %s", help_mode ? "<file-name>" : json_file.c_str()));
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}
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