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Merge https://github.com/cliffordwolf/yosys

This commit is contained in:
Andrew Zonenberg 2016-07-12 16:12:37 -07:00
parent 52a738a544 e92998a79c
commit 32bea97b75
1 changed files with 5 additions and 2 deletions
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7
passes/fsm/fsm_extract.cc
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@ -92,12 +92,15 @@ static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL
if (reset_state && RTLIL::SigSpec(*reset_state).is_fully_undef())
do {
SigSpec new_reset_state;
if (sig_aa.is_fully_def())
*reset_state = sig_aa.as_const();
new_reset_state = sig_aa.as_const();
else if (sig_bb.is_fully_def())
*reset_state = sig_bb.as_const();
new_reset_state = sig_bb.as_const();
else
break;
new_reset_state.extend_u0(GetSize(*reset_state));
*reset_state = new_reset_state.as_const();
log(" found reset state: %s (guessed from mux tree)\n", log_signal(*reset_state));
} while (0);