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Merge branch 'master' of github.com:cliffordwolf/yosys

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Clifford Wolf 2016-07-10 18:17:09 +02:00
parent 771c5fe000 307e31a95e
commit a72fb85dc2
1 changed files with 26 additions and 0 deletions
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26
techlibs/greenpak4/cells_sim.v
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@ -94,6 +94,32 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
endmodule
module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
input UP, input KEEP);
parameter RESET_MODE = "RISING";
parameter RESET_VALUE = "ZERO";
parameter COUNT_TO = 8'h1;
parameter CLKIN_DIVIDE = 1;
//more complex hard IP blocks are not supported for simulation yet
endmodule
module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
input UP, input KEEP);
parameter RESET_MODE = "RISING";
parameter RESET_VALUE = "ZERO";
parameter COUNT_TO = 14'h1;
parameter CLKIN_DIVIDE = 1;
//more complex hard IP blocks are not supported for simulation yet
endmodule
module GP_DELAY(input IN, output reg OUT);
parameter DELAY_STEPS = 1;