mirror of https://github.com/YosysHQ/yosys.git
Merge branch 'eddiehung-vtr'
This commit is contained in:
commit
b782076698
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@ -93,7 +93,7 @@ struct BlifDumper
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{
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std::string str = RTLIL::unescape_id(id);
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for (size_t i = 0; i < str.size(); i++)
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if (str[i] == '#' || str[i] == '=')
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if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>')
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str[i] = '?';
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cstr_buf.push_back(str);
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return cstr_buf.back().c_str();
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@ -104,14 +104,14 @@ struct BlifDumper
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cstr_bits_seen.insert(sig);
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if (sig.wire == NULL) {
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if (sig == RTLIL::State::S0) return config->false_type == "-" ? config->false_out.c_str() : "$false";
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if (sig == RTLIL::State::S1) return config->true_type == "-" ? config->true_out.c_str() : "$true";
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return config->undef_type == "-" ? config->undef_out.c_str() : "$undef";
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if (sig == RTLIL::State::S0) return config->false_type == "-" || config->false_type == "+" ? config->false_out.c_str() : "$false";
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if (sig == RTLIL::State::S1) return config->true_type == "-" || config->true_type == "+" ? config->true_out.c_str() : "$true";
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return config->undef_type == "-" || config->undef_type == "+" ? config->undef_out.c_str() : "$undef";
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}
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std::string str = RTLIL::unescape_id(sig.wire->name);
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for (size_t i = 0; i < str.size(); i++)
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if (str[i] == '#' || str[i] == '=')
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if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>')
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str[i] = '?';
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if (sig.wire->width != 1)
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@ -204,19 +204,25 @@ struct BlifDumper
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if (!config->impltf_mode) {
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if (!config->false_type.empty()) {
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if (config->false_type != "-")
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if (config->false_type == "+")
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f << stringf(".names %s\n", config->false_out.c_str());
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else if (config->false_type != "-")
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f << stringf(".%s %s %s=$false\n", subckt_or_gate(config->false_type),
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config->false_type.c_str(), config->false_out.c_str());
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} else
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f << stringf(".names $false\n");
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if (!config->true_type.empty()) {
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if (config->true_type != "-")
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if (config->true_type == "+")
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f << stringf(".names %s\n1\n", config->true_out.c_str());
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else if (config->true_type != "-")
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f << stringf(".%s %s %s=$true\n", subckt_or_gate(config->true_type),
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config->true_type.c_str(), config->true_out.c_str());
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} else
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f << stringf(".names $true\n1\n");
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if (!config->undef_type.empty()) {
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if (config->undef_type != "-")
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if (config->undef_type == "+")
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f << stringf(".names %s\n", config->undef_out.c_str());
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else if (config->undef_type != "-")
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f << stringf(".%s %s %s=$undef\n", subckt_or_gate(config->undef_type),
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config->undef_type.c_str(), config->undef_out.c_str());
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} else
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@ -456,7 +462,9 @@ struct BlifBackend : public Backend {
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log(" use the specified cell types to drive nets that are constant 1, 0, or\n");
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log(" undefined. when '-' is used as <cell-type>, then <out-port> specifies\n");
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log(" the wire name to be used for the constant signal and no cell driving\n");
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log(" that wire is generated.\n");
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log(" that wire is generated. when '+' is used as <cell-type>, then <out-port>\n");
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log(" specifies the wire name to be used for the constant signal and a .names\n");
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log(" statement is generated to drive the wire.\n");
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log("\n");
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log(" -noalias\n");
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log(" if a net name is aliasing another net name, then by default a net\n");
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