riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
4,764 Commits 106 Branches 49 Tags 45 MiB
Commit Graph

4764 Commits

Author SHA1 Message Date
Clifford Wolf 3be5aac52c
Merge pull request #953 from YosysHQ/clifford/fix948 
Add support for zero-width signals to Verilog back-end
 2019-04-22 20:01:09 +02:00
Clifford Wolf 0e0c80fac8 Add support for zero-width signals to Verilog back-end, fixes #948 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 19:44:42 +02:00
Clifford Wolf 9050b5e191
Merge pull request #950 from whitequark/attrmap_remove_wildcard 
attrmap: extend -remove to allow removing attributes with any value
 2019-04-22 16:54:38 +02:00
whitequark aeeefc32d8 attrmap: extend -remove to allow removing attributes with any value. 
Currently, `-remove foo` would only remove an attribute `foo = ""`,
which doesn't work on an attribute like `src` that may have any
value. Extend `-remove` to handle both cases. `-remove foo=""` has
the old behavior, and `-remove foo` will remove the attribute with
whatever value it may have, which is still compatible with the old
behavior.
 2019-04-22 14:18:15 +00:00
Clifford Wolf c0f9a74b12 Set ENABLE_LIBYOSYS=0 by default 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 14:59:30 +02:00
Clifford Wolf 93f32b5dec Set ENABLE_PYOSYS=0 by default 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 14:49:17 +02:00
Clifford Wolf 99d5435650
Merge pull request #905 from christian-krieg/feature/python_bindings 
Feature/python bindings
 2019-04-22 14:47:52 +02:00
Clifford Wolf 0e7901e45c
Merge pull request #941 from Wren6991/sim_lib_io_clke 
ice40 cells_sim.v: update clock enable behaviour based on hardware experiments
 2019-04-22 09:11:13 +02:00
Clifford Wolf c1dfc7ca96 Merge branch 'dh73-master' 2019-04-22 09:10:07 +02:00
Clifford Wolf 913659d644 Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master 2019-04-22 09:09:27 +02:00
Clifford Wolf cf1ba46fa0 Re-added clean after techmap in synth_xilinx 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 09:03:11 +02:00
Clifford Wolf cbd9b8a3f3
Merge pull request #916 from YosysHQ/map_cells_before_map_luts 
synth_xilinx to map_cells before map_luts
 2019-04-22 09:01:00 +02:00
Clifford Wolf 19fd411e77
Merge pull request #911 from mmicko/gowin-nobram 
Make nobram false by default for gowin
 2019-04-22 08:58:09 +02:00
Clifford Wolf b40af877f3
Merge pull request #909 from zachjs/master 
support repeat loops with constant repeat counts outside of constant functions
 2019-04-22 08:51:34 +02:00
Clifford Wolf a98b171814
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx 
Add pmux2shiftx command
 2019-04-22 08:39:37 +02:00
Clifford Wolf 632a666448
Merge pull request #945 from YosysHQ/clifford/libwb 
New behavior for read_verilog handling of whiteboxes
 2019-04-22 08:38:52 +02:00
Clifford Wolf 7b35d57592 Disable blackbox detection in techmap files 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-22 02:07:36 +02:00
Eddie Hung a3371e118b Merge branch 'master' into map_cells_before_map_luts 2019-04-21 14:24:50 -07:00
Luke Wren 71da836300 ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware experiments 2019-04-21 21:40:11 +01:00
Clifford Wolf d38f0c1a96 Fix tests 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-21 11:40:20 +02:00
Clifford Wolf 5b7fea5245 Add "noblackbox" attribute 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-21 11:40:09 +02:00
Clifford Wolf fb7f02be55 New behavior for front-end handling of whiteboxes 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 22:24:50 +02:00
Clifford Wolf f84a84e3f1
Merge pull request #943 from YosysHQ/clifford/whitebox 
[WIP] Add "whitebox" attribute, add "read_verilog -wb"
 2019-04-20 20:51:54 +02:00
Clifford Wolf fc23af1707 Auto-initialize OnehotDatabase on-demand in pmux2shiftx.cc 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 18:13:37 +02:00
Clifford Wolf 97e9caa4fa Add "onehot" pass, improve "pmux2shiftx" onehot handling 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 17:52:16 +02:00
Clifford Wolf f3ad8d680a Add "techmap -wb", use in formal flows 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 11:23:24 +02:00
Clifford Wolf b7445ef387 Check blackbox attribute in techmap/simplemap 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 11:10:05 +02:00
Clifford Wolf 5b915f0153 Add "wbflip" command 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 11:04:46 +02:00
Clifford Wolf e3687f6f4e
Merge pull request #942 from YosysHQ/clifford/fix931 
Improve proc full_case detection and handling
 2019-04-20 10:05:35 +02:00
Clifford Wolf b3a3e08e38 Improve "pmux2shiftx" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 02:03:44 +02:00
Clifford Wolf e06d158e8a Fix some typos 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 01:18:07 +02:00
Clifford Wolf 37728520a6 Improvements in "pmux2shiftx" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 01:15:48 +02:00
Clifford Wolf 0070184ea9 Improvements in pmux2shiftx 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 00:38:25 +02:00
Clifford Wolf 4c831d72ef Add test for pmux2shiftx 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 00:38:25 +02:00
Clifford Wolf 177878cbb0 Improve pmux2shift ctrl permutation finder 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 00:38:25 +02:00
Clifford Wolf 481f0015be Complete rewrite of pmux2shiftx 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 00:38:25 +02:00
Clifford Wolf 1bf8c2b823 Import initial pmux2shiftx from eddieh 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 00:38:25 +02:00
Clifford Wolf eafc4bd49f Improve "show" handling of 0/1/X/Z padding 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-20 00:37:43 +02:00
Clifford Wolf 148caecca3 Change "ne" to "neq" in btor2 output 
we need to do this because they changed the parser:
e97fc9ceda

Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-19 21:17:12 +02:00
Clifford Wolf ea2a21445e Add tests/aiger/.gitignore 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-19 14:04:12 +02:00
Eddie Hung 9dec3d9978 Spelling fixes 2019-04-19 14:00:22 +02:00
Eddie Hung 8f93999129 Revert "write_json to not write contents (cells/wires) of whiteboxes" 
This reverts commit 4ef03e19a8.
 2019-04-18 23:05:59 -07:00
Clifford Wolf e625324489 Update to ABC 3709744 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-18 21:25:02 +02:00
Eddie Hung b924923310
Merge pull request #917 from YosysHQ/eddie/fix_retime 
Retime by default when abc -dff
 2019-04-18 10:56:41 -07:00
Eddie Hung 4ef03e19a8 write_json to not write contents (cells/wires) of whiteboxes 2019-04-18 10:32:00 -07:00
Eddie Hung 290a798cec Ignore 'whitebox' attr in flatten with "-wb" option 2019-04-18 10:32:00 -07:00
Eddie Hung 070a2d2fd6 Fix abc's remap_name to not ignore [^0-9] when extracting sid 2019-04-18 09:55:03 -07:00
Eddie Hung 9aa94370a5 ABC to call retime all the time 2019-04-18 08:46:41 -07:00
Clifford Wolf f4abc21d8a Add "whitebox" attribute, add "read_verilog -wb" 
Signed-off-by: Clifford Wolf <clifford@clifford.at>
 2019-04-18 17:45:47 +02:00
Eddie Hung 6008bb7002 Revert "synth_* with -retime option now calls abc with -D 1 as well" 
This reverts commit 9a6da9a79a.
 2019-04-18 07:59:16 -07:00