mirror of https://github.com/YosysHQ/yosys.git
write_json to not write contents (cells/wires) of whiteboxes
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290a798cec
commit
4ef03e19a8
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@ -130,72 +130,75 @@ struct JsonWriter
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f << stringf(" }");
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first = false;
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}
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f << stringf("\n },\n");
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f << stringf("\n }");
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f << stringf(" \"cells\": {");
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first = true;
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for (auto c : module->cells()) {
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if (use_selection && !module->selected(c))
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continue;
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f << stringf("%s\n", first ? "" : ",");
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f << stringf(" %s: {\n", get_name(c->name).c_str());
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f << stringf(" \"hide_name\": %s,\n", c->name[0] == '$' ? "1" : "0");
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f << stringf(" \"type\": %s,\n", get_name(c->type).c_str());
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if (aig_mode) {
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Aig aig(c);
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if (!aig.name.empty()) {
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f << stringf(" \"model\": \"%s\",\n", aig.name.c_str());
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aig_models.insert(aig);
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if (!module->get_blackbox_attribute()) {
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f << stringf(",\n \"cells\": {");
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first = true;
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for (auto c : module->cells()) {
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if (use_selection && !module->selected(c))
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continue;
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f << stringf("%s\n", first ? "" : ",");
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f << stringf(" %s: {\n", get_name(c->name).c_str());
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f << stringf(" \"hide_name\": %s,\n", c->name[0] == '$' ? "1" : "0");
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f << stringf(" \"type\": %s,\n", get_name(c->type).c_str());
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if (aig_mode) {
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Aig aig(c);
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if (!aig.name.empty()) {
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f << stringf(" \"model\": \"%s\",\n", aig.name.c_str());
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aig_models.insert(aig);
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}
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}
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}
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f << stringf(" \"parameters\": {");
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write_parameters(c->parameters);
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f << stringf("\n },\n");
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f << stringf(" \"attributes\": {");
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write_parameters(c->attributes);
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f << stringf("\n },\n");
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if (c->known()) {
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f << stringf(" \"port_directions\": {");
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f << stringf(" \"parameters\": {");
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write_parameters(c->parameters);
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f << stringf("\n },\n");
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f << stringf(" \"attributes\": {");
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write_parameters(c->attributes);
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f << stringf("\n },\n");
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if (c->known()) {
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f << stringf(" \"port_directions\": {");
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bool first2 = true;
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for (auto &conn : c->connections()) {
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string direction = "output";
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if (c->input(conn.first))
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direction = c->output(conn.first) ? "inout" : "input";
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f << stringf("%s\n", first2 ? "" : ",");
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f << stringf(" %s: \"%s\"", get_name(conn.first).c_str(), direction.c_str());
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first2 = false;
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}
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f << stringf("\n },\n");
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}
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f << stringf(" \"connections\": {");
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bool first2 = true;
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for (auto &conn : c->connections()) {
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string direction = "output";
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if (c->input(conn.first))
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direction = c->output(conn.first) ? "inout" : "input";
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f << stringf("%s\n", first2 ? "" : ",");
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f << stringf(" %s: \"%s\"", get_name(conn.first).c_str(), direction.c_str());
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f << stringf(" %s: %s", get_name(conn.first).c_str(), get_bits(conn.second).c_str());
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first2 = false;
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}
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f << stringf("\n },\n");
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f << stringf("\n }\n");
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f << stringf(" }");
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first = false;
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}
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f << stringf(" \"connections\": {");
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bool first2 = true;
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for (auto &conn : c->connections()) {
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f << stringf("%s\n", first2 ? "" : ",");
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f << stringf(" %s: %s", get_name(conn.first).c_str(), get_bits(conn.second).c_str());
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first2 = false;
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}
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f << stringf("\n }\n");
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f << stringf(" }");
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first = false;
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}
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f << stringf("\n },\n");
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f << stringf("\n },\n");
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f << stringf(" \"netnames\": {");
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first = true;
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for (auto w : module->wires()) {
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if (use_selection && !module->selected(w))
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continue;
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f << stringf("%s\n", first ? "" : ",");
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f << stringf(" %s: {\n", get_name(w->name).c_str());
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f << stringf(" \"hide_name\": %s,\n", w->name[0] == '$' ? "1" : "0");
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f << stringf(" \"bits\": %s,\n", get_bits(w).c_str());
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f << stringf(" \"attributes\": {");
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write_parameters(w->attributes);
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f << stringf("\n }\n");
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f << stringf(" }");
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first = false;
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f << stringf(" \"netnames\": {");
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first = true;
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for (auto w : module->wires()) {
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if (use_selection && !module->selected(w))
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continue;
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f << stringf("%s\n", first ? "" : ",");
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f << stringf(" %s: {\n", get_name(w->name).c_str());
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f << stringf(" \"hide_name\": %s,\n", w->name[0] == '$' ? "1" : "0");
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f << stringf(" \"bits\": %s,\n", get_bits(w).c_str());
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f << stringf(" \"attributes\": {");
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write_parameters(w->attributes);
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f << stringf("\n }\n");
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f << stringf(" }");
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first = false;
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}
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f << stringf("\n }");
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}
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f << stringf("\n }\n");
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f << stringf("\n");
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f << stringf(" }");
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}
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