SergeyDegtyar
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d945b8a357
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Fix all comments from PR
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2019-08-21 21:52:07 +03:00 |
Eddie Hung
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c7af71ecde
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Use semicolon
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2019-08-21 11:47:17 -07:00 |
Eddie Hung
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5d0f6cbd54
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techmap before read
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2019-08-21 11:47:06 -07:00 |
Eddie Hung
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d4d692989a
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Merge remote-tracking branch 'origin/master' into xaig_arrival
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2019-08-21 11:39:20 -07:00 |
Eddie Hung
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8f69be9cc7
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Merge remote-tracking branch 'origin/master' into xaig_arrival
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2019-08-21 11:39:14 -07:00 |
Eddie Hung
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399ac760ff
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Output "h" extension only if boxes
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2019-08-21 11:31:18 -07:00 |
Eddie Hung
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8f0c1232d7
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Revert "Fix omode which inserts an output if none exists (otherwise abc9 breaks)"
This reverts commit 8182cb9d91 .
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2019-08-21 11:29:40 -07:00 |
Eddie Hung
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584c680691
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Add abc_arrival to SRL*
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2019-08-21 11:27:42 -07:00 |
Miodrag Milanovic
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948b6f91a1
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Fix test_pmgen deps
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2019-08-21 17:00:24 +02:00 |
Clifford Wolf
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7d8db1c053
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Merge pull request #1314 from YosysHQ/eddie/fix_techmap
techmap -max_iter to apply to each module individually
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2019-08-21 09:12:56 +02:00 |
SergeyDegtyar
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b835ec37cb
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Add temp directory
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2019-08-21 07:53:34 +03:00 |
Eddie Hung
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8182cb9d91
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Fix omode which inserts an output if none exists (otherwise abc9 breaks)
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2019-08-20 21:30:16 -07:00 |
Eddie Hung
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4d123b7638
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Revert "Only xaig if GetSize(output_bits) > 0"
This reverts commit 7b646101e9 .
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2019-08-20 21:22:38 -07:00 |
Eddie Hung
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7b646101e9
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Only xaig if GetSize(output_bits) > 0
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2019-08-20 20:57:13 -07:00 |
Eddie Hung
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076af2e617
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Missing newline
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2019-08-20 20:37:52 -07:00 |
Eddie Hung
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4cc74346f1
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Fix compile error
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2019-08-20 20:27:05 -07:00 |
Eddie Hung
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9b9d759451
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Fix copy-paste typo
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2019-08-20 20:18:51 -07:00 |
Eddie Hung
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b7a48e3e0f
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Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-08-20 20:18:17 -07:00 |
Eddie Hung
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64d62710de
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Oops
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2019-08-20 20:07:38 -07:00 |
Eddie Hung
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affe9c9c1a
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Merge branch 'eddie/fix_techmap' into xaig_arrival
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2019-08-20 20:06:47 -07:00 |
Eddie Hung
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fe61dcce8b
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Grammar
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2019-08-20 20:05:51 -07:00 |
Eddie Hung
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fce8dc7db2
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Add test
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2019-08-20 20:05:16 -07:00 |
Eddie Hung
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193eae0c84
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techmap -max_iter to apply to each module individually
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2019-08-20 19:50:20 -07:00 |
Eddie Hung
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57493e328a
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techmap -max_iter to apply to each module individually
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2019-08-20 19:48:16 -07:00 |
Eddie Hung
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c26c556384
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xilinx to use abc_map.v with -max_iter 1
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2019-08-20 19:47:11 -07:00 |
Eddie Hung
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6b1b03d9f7
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ecp5: remove DPR16X4 from abc_unmap.v
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2019-08-20 19:20:17 -07:00 |
Eddie Hung
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d46dc9c5b4
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ecp5 to use -max_iter 1
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2019-08-20 19:18:36 -07:00 |
Eddie Hung
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55acf3120f
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ecp5 to use abc_map.v and _unmap.v
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2019-08-20 18:59:03 -07:00 |
Eddie Hung
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4cd1d21bfe
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Add (* abc_arrival=<int> *) doc
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2019-08-20 18:27:16 -07:00 |
Eddie Hung
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343039496b
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Add reference to FD* timing
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2019-08-20 18:22:58 -07:00 |
Eddie Hung
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091bf4a18b
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Remove sequential extension
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2019-08-20 18:16:37 -07:00 |
Eddie Hung
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bbab608691
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Remove SRL* delays from cells_sim.v
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2019-08-20 18:14:40 -07:00 |
Eddie Hung
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fad15d276d
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retime_mode -> dff_mode
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2019-08-20 18:08:58 -07:00 |
Eddie Hung
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aa2d3af631
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LUTMUX -> LUTMUX6
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2019-08-20 18:08:07 -07:00 |
Eddie Hung
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30a379b5b6
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Cleanup techmap in map_luts
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2019-08-20 17:59:31 -07:00 |
Eddie Hung
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3b52d6e29c
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Move `techmap abc_map.v` into map_luts
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2019-08-20 17:55:12 -07:00 |
Eddie Hung
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54284aaa98
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Remove delays from abc_map.v
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2019-08-20 17:52:27 -07:00 |
Eddie Hung
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96f00e9147
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Typo
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2019-08-20 17:51:50 -07:00 |
Eddie Hung
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8f666ebac1
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Merge remote-tracking branch 'origin/master' into xaig_dff
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2019-08-20 17:36:14 -07:00 |
Eddie Hung
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1b5d2de1d4
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Do not sigmap!
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2019-08-20 15:23:26 -07:00 |
Eddie Hung
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0ca397f087
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Deprecate `abc_scc_break` attribute
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2019-08-20 15:10:01 -07:00 |
Eddie Hung
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e273ed5275
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Wrap SRL{16,32} too
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2019-08-20 15:09:38 -07:00 |
Eddie Hung
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808f07630f
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Wrap LUTRAMs in order to capture comb/seq behaviour
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2019-08-20 14:49:11 -07:00 |
Eddie Hung
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c00d72cdb3
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Minor refactor
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2019-08-20 14:47:58 -07:00 |
Eddie Hung
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0079e9b4a6
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Add LUTRAM delays
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2019-08-20 13:53:38 -07:00 |
Eddie Hung
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505d062daf
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Fix use of {CLK,EN}_POLARITY, also add a FIXME
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2019-08-20 13:33:31 -07:00 |
Eddie Hung
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8d0cffaf20
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Remove mapping rules
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2019-08-20 13:11:39 -07:00 |
Eddie Hung
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33960dd3d8
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Merge pull request #1209 from YosysHQ/eddie/synth_xilinx
[WIP] synth xilinx renaming, as per #1184
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2019-08-20 12:55:26 -07:00 |
Eddie Hung
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5eda5fc7eb
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Remove -icells
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2019-08-20 12:41:11 -07:00 |
Eddie Hung
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be9e4f1b67
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Use abc_{map,unmap,model}.v
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2019-08-20 12:39:11 -07:00 |