Clifford Wolf
362f4f996d
Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-11 15:07:29 +01:00
Clifford Wolf
1d148491c5
Merge pull request #1470 from YosysHQ/clifford/subpassdoc
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Add CodingReadme section on script passes
2019-11-10 11:00:38 +01:00
Clifford Wolf
65f197e28f
Add check for valid macro names in macro definitions
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-07 13:30:03 +01:00
Marcin Kościelnicki
c4bd318e76
synth_xilinx: Merge blackbox primitive libraries.
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First, there are no longer separate cell libraries for xc6s/xc7/xcu.
Manually instantiating a primitive for a "wrong" family will result
in yosys passing it straight through to the output, and it will be
either upgraded or rejected by the P&R tool.
Second, the blackbox library is expanded to cover many more families:
everything from Spartan 3 up is included. Primitives for Virtex and
Virtex 2 are listed in the Python file as well if we ever want to
include them, but that would require having two different ISE versions
(10.1 and 14.7) available when running cells_xtra.py, and so is probably
more trouble than it's worth.
Third, the blockram blackboxes are no longer in separate files — there
is no practical reason to do so (from synthesis PoV, they are no
different from any other cells_xtra blackbox), and they needlessly
complicated the flow (among other things, merging them allows the user
to use eg. Series 7 primitives and have them auto-upgraded to
Ultrascale).
Last, since xc5v logic synthesis appears to work reasonably well
(the only major problem is lack of blockram inference support), xc5v is
now an accepted setting for the -family option.
2019-11-06 15:11:27 +01:00
Clifford Wolf
5110a34dd7
Fix write_aiger bug added in 524af21
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-11-04 14:25:13 +01:00
Clifford Wolf
c3ad375200
Add CodingReadme section on script passes
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-31 10:46:20 +01:00
Clifford Wolf
81876a3734
Merge pull request #1393 from whitequark/write_verilog-avoid-init
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write_verilog: do not print (*init*) attributes on regs
2019-10-27 10:25:01 +01:00
Clifford Wolf
84982b3083
Improve naming scheme for (VHDL) modules imported from Verific
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-24 12:13:50 +02:00
David Shah
34dadd9ab2
Merge pull request #1455 from YosysHQ/dave/ultrascaleplus
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Add BRAM and URAM mapping for UltraScale[+]
2019-10-24 08:14:20 +01:00
Clifford Wolf
d49c6b2cba
Add "verific -L"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-24 09:14:03 +02:00
David Shah
3506eaf290
xilinx: Add URAM288 mapping for xcup
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-23 11:47:44 +01:00
David Shah
6769d31ddb
xilinx: Add support for UltraScale[+] BRAM mapping
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Signed-off-by: David Shah <dave@ds0.me>
2019-10-23 11:47:37 +01:00
Clifford Wolf
f02623abb5
Bugfix in smtio vcd handling of $-identifiers
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-23 00:04:34 +02:00
Marcin Kościelnicki
7b350cacd4
xilinx: Support multiplier mapping for all families.
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This supports several older families that are not yet supported for
actual logic synthesis — the intention is to add them soon.
2019-10-22 18:06:57 +02:00
Clifford Wolf
a3a7bb9bf7
Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg
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Call memory_dff before DSP mapping to reserve registers (fixes #1447 )
2019-10-22 17:36:54 +02:00
Clifford Wolf
5025aab8c9
Add "verilog_defines -list" and "verilog_defines -reset"
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-21 13:35:56 +02:00
Clifford Wolf
4033ff8c2e
Fix handling of "restrict" in Verific front-end
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Signed-off-by: Clifford Wolf <clifford@clifford.at>
2019-10-21 12:39:28 +02:00
David Shah
fa989e59e5
ecp5: Pass -nomfs to abc9
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Fixes #1459
Signed-off-by: David Shah <dave@ds0.me>
2019-10-20 10:30:41 +01:00
Miodrag Milanović
f2aa2d1bb4
Merge pull request #1457 from xobs/python-binary-name
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Makefile: don't assume python is called `python3`
2019-10-19 08:58:02 +02:00
Sean Cross
82f60ba938
Makefile: don't assume python is called `python3`
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On some architectures, notably on Windows, the official name for the
Python binary from python.org is `python`. The build system assumes
that python is called `python3`, which breaks under this architecture.
There is already infrastructure in place to determine the name of the
Python binary when building PYOSYS. Since Python is now always required
to build Yosys, enable this check universally which sets the
`PYTHON_EXECUTABLE` variable.
Then, reuse this variable in other Makefiles as necessary, rather than
hardcoding `python3` everywhere.
Signed-off-by: Sean Cross <sean@xobs.io>
2019-10-19 14:04:52 +08:00
Miodrag Milanović
e8ef3fcdfc
Merge pull request #1454 from YosysHQ/mmicko/common_tests
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Share common tests
2019-10-18 14:29:44 +02:00
Miodrag Milanovic
190b40341a
fixed error
2019-10-18 13:15:36 +02:00
Miodrag Milanovic
9bd9db56c8
Unify verilog style
2019-10-18 12:50:24 +02:00
Miodrag Milanovic
12383f37b2
Common memory test now shared
2019-10-18 12:33:35 +02:00
Miodrag Milanovic
477702b8c9
Remove not needed tests
2019-10-18 12:20:35 +02:00
Miodrag Milanovic
5603595e5c
Share common tests
2019-10-18 12:19:59 +02:00
Miodrag Milanovic
ab98f2dccf
fix yosys path
2019-10-18 11:18:53 +02:00
Miodrag Milanovic
56f9482675
Fix path to yosys
2019-10-18 11:12:03 +02:00
Miodrag Milanovic
c2ec7ca703
Moved all tests in arch sub directory
2019-10-18 11:06:12 +02:00
Miodrag Milanovic
3c41599ee1
Add async2sync
2019-10-18 11:00:27 +02:00
Miodrag Milanović
0568920d79
Merge pull request #1435 from YosysHQ/mmicko/efinix
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Add tests for Efinix architecture (contd)
2019-10-18 10:54:35 +02:00
Miodrag Milanović
b4d7650548
Merge branch 'master' into mmicko/efinix
2019-10-18 10:54:28 +02:00
Miodrag Milanović
ab4899a2d0
Merge pull request #1434 from YosysHQ/mmicko/anlogic
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Add tests for Anlogic architecture (contd)
2019-10-18 10:54:04 +02:00
Miodrag Milanović
66fca65b58
Merge branch 'master' into mmicko/anlogic
2019-10-18 10:53:56 +02:00
Miodrag Milanović
5ffb0053ec
Merge pull request #1421 from YosysHQ/eddie/pr1352
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Add tests for ECP5 architecture (contd)
2019-10-18 10:53:34 +02:00
Miodrag Milanović
0b0b0cc0d9
Merge branch 'master' into eddie/pr1352
2019-10-18 10:52:50 +02:00
Miodrag Milanović
e0a67fce12
Merge pull request #1420 from YosysHQ/eddie/pr1363
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Add tests for Xilinx architecture (contd)
2019-10-18 10:51:32 +02:00
Miodrag Milanovic
b659082e4a
hierarchy - proc reorder
2019-10-18 09:13:06 +02:00
Miodrag Milanovic
46af9a0ff7
hierarchy - proc reorder
2019-10-18 09:06:43 +02:00
Miodrag Milanovic
0d60902fd9
hierarchy - proc reorder
2019-10-18 09:04:02 +02:00
Miodrag Milanovic
e6ad714d20
hierarchy - proc reorder
2019-10-18 08:06:57 +02:00
N. Engelhardt
3b405d985e
Call memory_dff before DSP mapping to reserve registers ( fixes #1447 )
2019-10-17 21:33:54 +02:00
Miodrag Milanovic
980df499ab
Make equivalence work with latest master
2019-10-17 17:24:53 +02:00
Miodrag Milanovic
b2f0d75807
remove not needed top module
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
1a399c6456
remove not needed top module
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
a198bcdd4f
split muxes synth per type
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
36af102801
Test dffs separetely
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
487b38b124
Split latches into separete tests
2019-10-17 17:11:11 +02:00
Miodrag Milanovic
fba6229718
Fix formatting
2019-10-17 17:10:42 +02:00
Miodrag Milanovic
53bc499a90
Clean verilog code from not used define block
2019-10-17 17:10:42 +02:00